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參數(shù)資料
| 型號： | TPS65040ZQER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA71 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, GREEN, PLASTIC, MICRO, BGA-71 |
| 文件頁數(shù)： | 66/73頁 |
| 文件大小： | 1928K |
| 代理商： | TPS65040ZQER |
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CSPI Read Operation
CDATA
CCLK
CSTB
A6
A7
A5
A4
A3
A2
A1
A0
D6
D7
D5
D4
D3
D2
D1
D0
CDATA DirectionChange
fromOutputtoInput
CDATA DirectionChange
fromInputtoOutput
1.5CCLK
tcymc
twlmc
twhmc
tDS
tDH
tSD
twhms
tpSLH
tpSHL
tpHL
tpLH
CDATA
CCLK
CSTB
TSP
SLVS708B – NOVEMBER 2006 – REVISED APRIL 2007
In a READ operation, the 8-Bit advance data becomes the address, and the next 8-Bit group becomes the
READ operation. The CSTB must be input after the address of 8-Bit advance data. CDATA pin condition
remains in input mode until the falling edge of CSTB is input. Do not input CCLK and CDATA when CSTB is
high. CDATA pin changes from the input mode to the output mode at the falling edge of CSTB. At the falling
edge of CSTB, the data from CDATA pin is output, starting from MSB data. The next data will be read one by
one at the falling edge of CCLK. CDATA pin returns from the output mode to the input mode after CCLK inputs 8
clocks.
Figure 87. CSPI Read Format
Table 25 shows a register written, RESERVED in register map of CSPI. There are both registers for
READ/WRITE. Even if data is written in the register for WRITE, the TPS65040 is not affected at all, and the
TPS65040 continues the same operation before data is written. DATA doesn't change into the state of the
output by the falling edge of CSTB, even if data is read from the READ register. The data is not output from
TPS65040, and the CDATA pin maintains the input.
Figure 88. CSPI Timing
TSP is the interface that consists of three lines (TSPDIN pin, TSPCLK pin, and TSPEN pin as input). Data
length is 16-BIT (12-BIT data, and 4-BIT address). Figure 89 shows WRITE format, while Figure 90 shows the
WRITE timing of TSP. In a WRITE operation the first 4 BITs are the address bits, followed by 12 BITs of data.
When TSPEN is low the address and data are taken by the rising edge of TSPCLK, and reflected by the rising
edge of TSPEN. The register that TSP can control becomes AFCDATA, 2GLDOCTRL, and AFCDACCTL.
69
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