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參數資料
型號: TPS65040ZQER
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA71
封裝: 5 X 5 MM, 0.50 MM PITCH, GREEN, PLASTIC, MICRO, BGA-71
文件頁數: 62/73頁
文件大小: 1928K
代理商: TPS65040ZQER
HOT-DIE DETECTION
SEQUENCE CONTROL
Power Up Sequence
Asynchronous Input of CRESET
Power Supply Input Order and Level for VBN1, VBN2, VBN3, VBN4, VBN5, DDINA and VBDDP
Power-Up Mode
SLVS708B – NOVEMBER 2006 – REVISED APRIL 2007
TPS65040 provides hot-die detection as a function of junction temperature. It is expressed as 3-BIT data
representing rising junction temperatures of 110
°C, 120°C, 130°C, 140°C, and 150°C. The 3-BIT data can be
read via the serial interface. This function does not cause block shutoff (as in a thermal shutdown condition), but
furnishes junction temperature data. Table 23 shows the 3-BIT threshold temperatures.
Table 23. Threshold Temperature
E6h:TEMP[2:0]
TEMPERATURE
000
Reserved
001
Reserved
010
Under 110
°C
011
110
°C ± 15°C
100
120
°C ± 15°C
101
130
°C ± 15°C
110
140
°C ± 15°C
111
150
°C ± 15°C
TSD Shutdown
160
°C ± 15°C
The TPS65040 is designed to permit the power-up sequence shown in Figure 84. The sequences have the
following relationship:
1. REG_EN=Low: TPS65040 power down
2. REG_EN=High: VGGE1_V28, VGGE2_V28, and VGGE3_V28 are powered up in Normal Mode.
3. VIO1V8=High: V12_V28RX, V13_V28A, V15_V18 are powered up in Normal Mode.
4. SYSCLK_EN=High: VTCXO, AFCDAC, CLOCK DISTRIBUTION (SIIN_SYSCLK1) are powered up. When
VTCXO is powered up, the VCTCXO is supplied from VTCXO, and oscillation starts.
5. CRESET=High: V12_V28RX, V13_V28A, and V15_V18A change into low-power mode. The serial
interface accepts data from the host CPU.
6. The oscillation of VCTCXO is steady.
7. Operation Starts (See Power-Up Mode below).
The TPS65040 accepts an asynchronous input of CRESET. If it is SYSCLK_EN=High as shown in Figure 85, it
is possible to make the clock output from TPS65040 work without stopping. However, the block which is
powered up or powered down by the register should note it so that all registers become the default values.
The TPS65040 has seven power supply input pins. The order of input does not matter. Power up all power pins
simultaneously. The power supply level for VBN1, VBN2, VBN3, VBN4, VBN5, DDINA and VBDDP should be
the same level, as much as possible.
This mode is only valid in the power-up sequence, which is shown by Figure 84. After a valid power-up
sequence, the TPS65040 supplies the clock, and accepts serial interface communication from the host CPU.
The TSP65040 then changes the mode to 2G mode, 3G mode, low-power mode, or no communication mode.
Power-up mode is not a steady (i.e., continuous) mode.
65
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