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參數資料
| 型號： | TPS65040ZQER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA71 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, GREEN, PLASTIC, MICRO, BGA-71 |
| 文件頁數： | 54/73頁 |
| 文件大小： | 1928K |
| 代理商： | TPS65040ZQER |
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AFCDAC
12BIT DAC
r[AFCDAT A<11:0>]
+
-
AFC
SYSCLK_EN
3.05VLDO
CCLK
CDATA
CSTB
SerialInterface
COVREF2
0.1uF
VREF2
VREF2Buffer
Amplifier
REFERENCEBLOCK
TSPCLK
TSPDIN
TSPEN
r[PSCNTAFC]
Enable
GND1
VBN1
SLVS708B – NOVEMBER 2006 – REVISED APRIL 2007
AFCDAC is a 12-bit DAC that can be used for the adjustment of VCTCXO oscillation frequency. Figure 80
shows a block diagram. AFCDAC controls the on/off switch based on SYSCLK_EN pin and r[PSCNTAFC].
Register command r[PSCNTAFC] can be controlled through the serial interface; default is High. The output
voltage is controlled by registers named AFCMSB and AFCLSB. The output voltage corresponds to the data of
r[AFCMSB] and r[AFCLSB]. The r[AFCMSB] and r[AFCLSB] registers can be controlled through the serial
interface, and default is 800h. AFCDAC can be controlled by both CSPI and TSP interfaces. When the output
voltage changes from CSPI interface, the first access register must be the r[AFCMSB], then the r[AFCLSB] next.
If it is not in the correct order the output voltage can not change the value. When the output voltage changes
from TSP interface, it can be one-time accessing. It does not need two-time accessing, like the CSPI interface.
More detail is given in the SERIAL INTERFACE Section. Table 14 shows AFCDAC control. As for AFCDAC, it is
a pull down in SYSCLK_EN=Low or r[PSCNTAFC]=Low to turn off to GND. When AFCDAC is powered up by
SYSCLK_EN=Low to High, (r[PSCNTAFC]=High) or r[PSCNTAFC]=Low to High (SYSCLK_EN=High) from
power down, the output voltage is kept at the same voltage before power down by the r[AFCMSB] and
r[AFCLSB] registers. But the CRESET pin goes low, or REG_EN pin goes low, the r[AFCMSB] and r[AFCLSB]
registers are reset, and the output voltage returns to the default voltage. Note that the electrical characteristics of
AFCDAC are not assured within the range of 2.7V<VBAT<3.1V function. Moreover, the output voltage
decreases when VBAT decreases according to the output voltage. Turn AFCDAC off when not in use.
Figure 80. AFCDAC Block Diagram
58
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