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參數(shù)資料
| 型號： | TPS65040ZQER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA71 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, GREEN, PLASTIC, MICRO, BGA-71 |
| 文件頁數(shù)： | 50/73頁 |
| 文件大?。?/td> | 1928K |
| 代理商： | TPS65040ZQER |
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VGGE2_V28
VGGE3_V28
SLVS708B – NOVEMBER 2006 – REVISED APRIL 2007
Table 9. VGGE1_V28 ON/OFF and Normal Mode/Low Power Mode Control
REG_EN(1)
r[PSCNTGGE1]
r[GGEmodecnt]
r[GGE1psmode]
SYSCLK_EN2
VGGE1_V28
1
VIO1V8 is off
Don't Care
Normal Mode
1
Don't Care
Normal Mode
1
0
Don't Care
Low Power Mode
1
0
Don't Care
1
Normal Mode
1
0
Don't Care
0
Low Power Mode
0
1
Don't Care
OFF
1
0
Don't Care
OFF
0
Don't Care
OFF
(1)
REG_EN sequence is described in SEQUENCE CONTROL.
VGGE2_V28 is an LDO that outputs 2.85 V, and is one of the LDOs enabled during the power-up sequence of
the TPS65040. More detail is given in the SEQUENCE CONTROL Section. Normal mode and low-power mode
can be selected, with normal mode being the high-performance mode, and low-power mode for low current
consumption. The output PMOS is stopped when the load current exceeds the limit value for the current-limit
protection circuit in normal mode, and the power supply is shut down. When the load current falls below the limit
value, current limit is released. Current limit protection is not available in low-power mode. This LDO has a
low-current mode and a high-current mode in normal mode. The low-current mode and high-current mode
correspond to light-load and heavy-load conditions, respectively. The modes are changed automatically. LDO
on/off is controlled by register command r[PSCNTGGE2]. Normal mode and low-power mode are switched using
register command r[GGE2psmode] at r[GGEmodecnt]=High , SYSCLK_EN2 pin at r[GGEmodecnt]=Low.
Register commands r[PSCNTGGE2], r[GGEmodecnt], and r[GGE2psmode] are controlled through the serial
interface; the default is 1. Note that the electrical characteristics of this LDO are not assured within the range of
3 V <VBAT<3.1V function. Moreover, the output voltage also decreases by VBAT–VSAT when VBAT decreases.
Turn off this LDO, or use the low-power mode ,when in the VBAT<3 V condition. On/off control of
VGGE2_V28A, and the switch control of normal mode/low-power mode are shown in Table 10.
Table 10. VGGE2_V28 ON/OFF and Normal Mode/Low Power Mode Control
REG_EN(1)
r[PSCNTGGE2]
r[GGEmodecnt]
r[GGE2psmode]
SYSCLK_EN2
VGGE2_V28
1
VIO1V8 is off
Don't Care
Normal Mode
1
Don't Care
Normal Mode
1
0
Don't Care
Low Power Mode
1
0
Don't Care
1
Normal Mode
1
0
Don't Care
0
Low Power Mode
0
1
Don't Care
OFF
1
0
Don't Care
OFF
0
Don't Care
OFF
(1)
REG_EN sequence is described in SEQUENCE CONTROL.
VGGE3_V28 is an LDO that outputs 2.85 V, and powers up with the power-up sequence of the TPS65040. More
detail is found in the SEQUENCE CONTROL Section. Normal mode and low-power mode can be selected.
Normal mode provides high performance, and low-power mode offers low current consumption. Output PMOS is
stopped when the load current exceeds the limit value of the current limit protection circuit in normal mode, and
the power supply is shut down. When the load current falls below the limit values, current limit is released.
Current-limit protection is not available in low-power mode. This LDO has a low-current mode and a high-current
mode in normal mode. The low-current mode and high-current mode correspond to light-load and heavy-load
conditions, respectively. The modes are changed automatically. The LDO on/off is controlled by register
command r[PSCNTGGE3]. Normal mode and low-power mode are switched using register command
r[GGE3psmode] at r[GGEmodecnt]=High , SYSCLK_EN2 pin at r[GGEmodecnt]=Low. Register commands that
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