
LDO OFF
LDO ON
LDO_EN = 1
LDO_EN = 0
POWER DOWN
|| = OR
& = AND
(
?) = rising edge
(
?) = falling edge
V
=
(V
- V
) + V
+ V
SHUNT
CSIN
CSOUT
ZERO
OFFSET
25
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SLVSA48 – APRIL 2010
Figure 55. State Diagram for the HV LDO
INTERRUPT PIN
The interrupt pin is used to signal any fault condition to the host processor. Whenever a fault occurs in the IC the
corresponding fault bit is set in the INT1, INT2, or INT3 register, and the open-drain output is pulled low. The INT
pin is released (returns to HiZ state) if any of the INT1, INT2, INT3 registers is accessed by the host but fault bits
are cleared only by reading the INTx register containing the bit. However, if a failure persists, the corresponding
interrupt bit remains set but no new interrupt is issued. The TSD bit (thermal shutdown) is auto cleared which
means that the bit is reset to 0 automatically after the chip has cooled down below the thermal shutdown release
threshold.
The MASK1, MASK2, and MASK3 registers are used to mask certain events or group of events from generating
interrupts. The MASKx settings affect the INT pin only and have no impact on protection and monitor circuits
themselves.
CURRENT SHUNT MONITOR
TPS65230 offers an integrated high-precision current shunt monitor to measure battery charging and discharging
currents. The inputs of a low-offset amplifier are connected across an external low-value shunt resistor. This
shunt voltage is gained up by a factor of 25 and added to a reference voltage connected to the VZERO terminal.
VSHUNT > VZERO for currents flowing into the battery and VSHUNT < VZERO for currents flowing out of the battery.
The reference voltage is buffered by a low-offset, high impedance input buffer.
(6)
Where:
1. VSHUNT is the output voltage of the current shunt monitor
2. VCSIN is the charger side of the shunt resistor
3. VCSOUT is the battery side of the shunt resistor
4. VZERO is the 0-current reference voltage
5. VOFFSET is the offset of the differential amplifier
The offset of the differential amplifier introduces a measurement error of ±40 V input referred, equivalent to ±2
mA assuming a 20-m
Ω shunt resistor which can be calibrated out be the system.
The shunt monitor is disabled by default and can be enabled by the host by setting the SMON_EN bit in the
CONTROL register to 1.
Copyright 2010, Texas Instruments Incorporated
37