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參數資料
| 型號： | TRCV0110G |
| 英文描述： | ATM/SONET DEMULTIPLEXER|BIPOLAR|BGA|177PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的分路器|雙極|的BGA | 177PIN |塑料 |
| 文件頁數： | 11/26頁 |
| 文件大小： | 476K |
| 代理商： | TRCV0110G |
Agere Systems Inc.
11
Data Sheet
March 28, 2002
Clock Recovery, 1:16 Data Demultiplexer
TRCV0110G 10 Gbits/s Limiting Amplifier
Functional Overview
The TRCV0110G performs the data detection, clock recovery, and 1:16 demultiplexing operations required to
support 10 Gbits/s
1
OC-192/STM-64 applications compliant with
Telcordia Technologies
and ITU standards. One
of two high-speed inputs can be selected as the data source. A PLL recovers the clock which is used to retime the
data. A 1:16 data demultiplexer performs the serial-to-parallel conversion and generates 16 parallel outputs at a
622 Mbits/s. The parallel output data is aligned to a 622 MHz clock derived from the 10 GHz recovered clock.
FEC Rate Support
The TRCV0110G will support both the normal OC-192/STM-64 rate of 9.9532 GHz and the forward error
correction (FEC) rate of 10.7092 GHz. The FECN pin selects the rate range at which the part is operated.
Throughout this document, the specifications are given in terms of the normal operating rate only. All frequency-
based specifications are to be multiplied by the appropriate scaling factor when not operating at the OC-192/
STM64 rate. All time-based specifications, with the exception of electrical signal rise and fall times, are also to be
multiplied by the appropriate scaling factor. For example, a reference clock would need to be applied at
167.33 MHz or 669.32 MHz (a multiplication factor of 255/237) for the parallel data interface to operate at
669.32 MHz when FECN = 0.
High-Speed Data Inputs
Limiting Amplifier Operation
The TRCV0110G data input circuit contains a limiting amplifier that has approximately 40 dB of voltage gain. As
shown in Figure 3, the DATAP/N inputs should be ac-coupled. These ac-coupling capacitors are typically included
inside the optical receiver package. For applications requiring ac-coupling external to the O/E device, insert low
ESR 0.047
μ
F capacitors in the transmission line path. These capacitors should be chosen such that their size is
similar to the transmission line width in order to minimize the parasitic effects of larger than necessary pad sizes.
The 50
transmission lines are terminated with on-chip 50
resistors. The ACM pin should be connected with a
low inductance, low ESR 0.047
μ
F capacitor to ground. This capacitor provides an RF bypass for common-mode
noise that may be present on the data input pins. This capacitor as well as V
CCLA
decoupling capacitors should be
mounted as close as possible to the device package to avoid excess board trace inductance. Please refer to
Table 13 on page 18
,
for input sensitivity and other critical input specifications.
0364.a(F)
Figure 3. Data Input Circuit
1. The OC-192/STM-64 data rate of 9.95328 Gbits/s is typically approximated as 10 Gbits/s in this document when referring to the application
rate. Similarly, the low-speed parallel interface data rate of 622.08 Mbits/s is typically approximated as 622 Mbits/s. The exact frequencies
are used only when necessary for clarity.
50
50
INPUT
BIAS
DATAP
DATAN
ACM
0.047
μ
F
0.047
μ
F
FROM
TIA
LIMITING
AMPLIFIER
0.047
μ
F
0.1
μ
F
V
CCLA
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