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參數資料
| 型號： | TRCV0110G |
| 英文描述： | ATM/SONET DEMULTIPLEXER|BIPOLAR|BGA|177PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的分路器|雙極|的BGA | 177PIN |塑料 |
| 文件頁數： | 12/26頁 |
| 文件大小： | 476K |
| 代理商： | TRCV0110G |
12
Agere Systems Inc.
Data Sheet
March 28, 2002
Clock Recovery, 1:16 Data Demultiplexer
TRCV0110G 10 Gbits/s Limiting Amplifier
High-Speed Data Inputs
(continued)
Loopback Data Input
The second high-speed input in the TRCV0110G is for system loopback operation. When mated with Agere’s
TTRN0110G, the high-speed loopback data output can be direct coupled into the TRCV0110G loopback data input
pins LBDP and LBDN. During this mode of operation, parallel low-speed data coming from the users application
(typically a line card or transponder module) can be serialized through the TTRN0110G and redirected through the
high-speed loopback data input port of the TRCV0110G. The TRCV0110G would then recover the clock and dese-
rialize the data to be received by the users application. The loopback data flow is controlled by the ENLBDN pins
on both devices.
0366.a(F)
Figure 4. Loopback Data Input Circuit
Clock Recovery Operation
The clock and data recovery (CDR) circuit uses a PLL to extract the clock and retime the 10 Gbits/s data. The
TRCV0110G uses an external loop filter that is described below in Figure 5. A 622 MHz clock derived from the
recovered clock is available as an output at CK622P/N. A 622 MHz or 155 MHz clock derived from the recovered
clock is available as an auxiliary output at CKOP/N.
2245(F)
Figure 5. TRCV0110G Loop Filter
LBDP
50
50
V
CCD
LBDN
FROM TTRN0110G
LOOPBACK OUTPUTS
LOOPBACK
INPUT
160
V
CCA
5 pF
V
CCA
5 pF
0.01
μ
F
PLL
LFP
LFN
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