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參數資料
| 型號： | TRCV0110G |
| 英文描述： | ATM/SONET DEMULTIPLEXER|BIPOLAR|BGA|177PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的分路器|雙極|的BGA | 177PIN |塑料 |
| 文件頁數： | 8/26頁 |
| 文件大小： | 476K |
| 代理商： | TRCV0110G |
8
Agere Systems Inc.
Data Sheet
March 28, 2002
Clock Recovery, 1:16 Data Demultiplexer
TRCV0110G 10 Gbits/s Limiting Amplifier
Ball Information
(continued)
Ball Description
(continued)
Note:
In Table 3, when operating the TRCV0110G device at the OC-192/STM-64 rate, 155 Mbits/s should be
interpreted as 155.52 Mbits/s. When operating the TRCV0110G device at the RS FEC OC-192/STM-64
rate, 155 Mbits/s should be interpreted as 167.33 Mbits/s.
Table 3. Ball Descriptions—622.08 Mbits/s and Related Signals
Ball
Symbol
*
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
I = input, O = output. I
u
= an internal pull-up resistor on this pin, I
d
= an internal pull-down resistor on this pin, I
t
= an internal termination
resistance of 50
on this pin.
Type
Level
Name/Description
L9
M9
P9
N9
P8
N8
M7
N7
P6
P7
N6
M6
N5
P5
N4
P4
L4
M4
N3
P3
M2
N2
L1
M1
J1
K1
G1
H1
E2
E1
D2
D1
D15P
D15N
D14P
D14N
D13P
D13N
D12P
D12N
D11P
D11N
D10P
D10N
D9P
D9N
D8P
D8N
D7P
D7N
D6P
D6N
D5P
D5N
D4P
D4N
D3P
D3N
D2P
D2N
D1P
D1N
D0P
D0N
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Data Output (622 Mbits/s).
622 Mbits/s differential data output.
D15 is the most significant bit and is the first received on the
DATAP/N or LBDP/N input.
Note:
This data rate will scale when operating at different rates.
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