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參數資料
| 型號： | TRCV0110G |
| 英文描述： | ATM/SONET DEMULTIPLEXER|BIPOLAR|BGA|177PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的分路器|雙極|的BGA | 177PIN |塑料 |
| 文件頁數： | 9/26頁 |
| 文件大小： | 476K |
| 代理商： | TRCV0110G |
Agere Systems Inc.
9
Data Sheet
March 28, 2002
Clock Recovery, 1:16 Data Demultiplexer
TRCV0110G 10 Gbits/s Limiting Amplifier
Ball Information
(continued)
Ball Description
(continued)
Table 3. Ball Descriptions—622.08 Mbits/s and Related Signals
(continued)
Ball
Symbol
*
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
I = input, O = output. I
u
= an internal pull-up resistor on this pin, I
d
= an internal pull-down resistor on this pin, I
t
= an internal termination
resistance of 50
on this pin.
Type
I
u
Level
Name/Description
B1
MUTEDMXN
CMOS
Mute DeMUX Parallel Output Data (Active-Low).
Forces all
demultiplexer output data D[15:0] to a logic-low level.
0 = Demultiplexer output muted.
1 or no connection = Normal operation.
Mute CK622P/N Clock Output (Active-Low).
Forces
CK622P/N to logic low when MUTE622N is active.
0 = Muted.
1 or no connection = Enabled.
CKO Frequency Select.
Selects 155 MHz or 622 MHz clock
frequency on CLKOP/N.
0 = 155 MHz CKOP/N.
1 or no connection = 622 MHz CKOP/N.
Mute CKOP/N Clock Output (Active-Low).
Forces CKOP/N
to logic low when MUTECKON is active.
0 = Muted.
1 or no connection = Enabled.
Reference Frequency Select.
Sets clock and data recovery
(CDR) PLL to accept 155 MHz, or 622 MHz reference
frequency on REFCLKP/N.
0 = 155 MHz REFCLKP/N.
1 or no connection = 622 MHz REFCLKP/N.
Reference Clock Input (155 MHz, or 622 MHz).
B5
MUTE622N
I
u
CMOS
A5
FREQCKO
I
u
CMOS
B4
MUTECKON
I
u
CMOS
A4
REFFREQ
I
u
CMOS
P12
N12
REFCLKP
REFCLKN
I
LVDS
Note:
This clock frequency
must
scale when operating at
different rates.
Recovered Clock Output (622 MHz).
622 MHz recovered
differential clock output. Pins are active but forced to
differential logic low when MUTE622N = 0.
P11
N11
CK622P
CK622N
O
LVDS
Note:
This clock frequency will scale when operating at
different rates.
Recovered Clock Output (155 MHz or 622 MHz).
Selectable 155 MHz or 622 MHz recovered differential clock
output. Pins are active but forced to differential logic low
when MUTECKON = 0.
P10
N10
CKOP
CKON
O
LVDS
Note:
These clock frequencies will scale when operating at
different rates. Use the FREQCKO pin to select the
frequency.
Resistor Reference LVDS.
LVDS bias reference resistor.
Connect a 1.5 k
resistor to V
CCD
.
Amplifier Common Mode.
Input amplifier common bias
point. Place a 0.047 μF RF bypass capacitor to GND.
C2
RREFLVDS
I
Analog
D9
ACM
I
Analog
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