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參數(shù)資料
| 型號(hào)： | TRCV0110G |
| 英文描述： | ATM/SONET DEMULTIPLEXER|BIPOLAR|BGA|177PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的分路器|雙極|的BGA | 177PIN |塑料 |
| 文件頁(yè)數(shù)： | 7/26頁(yè) |
| 文件大小： | 476K |
| 代理商： | TRCV0110G |
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Agere Systems Inc.
7
Data Sheet
March 28, 2002
Clock Recovery, 1:16 Data Demultiplexer
TRCV0110G 10 Gbits/s Limiting Amplifier
Ball Information
(continued)
Ball Description
Note:
In Table 2, when operating the TRCV0110G device at the OC-192/STM-64 rate, 10 Gbits/s should be
interpreted as 9.95328 Gbits/s. When operating the TRCV0110G device at the RS FEC OC-192/STM-64
rate, 10 Gbits/s should be interpreted as 10.709 Gbits/s. When operating the TRCV0110G device at the
Ethernet rate, 10 Gbits/s should be interpreted as 10.3125 Gbits/s.
Table 2. Ball Descriptions—10 Gbits/s and Related Signals
Ball
Symbol
*
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
I = input, O = output. I
u
= an internal pull-up resistor on this pin, I
d
= an internal pull-down resistor on this pin, I
t
= an internal termination
resistance of 50
on this pin.
Type
I
t
Level
Name/Description
A9
A7
DATAP
DATAN
High-speed
Analog
Limiting Amp Input for 10 Gbits/s CML.
Primary data input.
Note:
This data input will scale when operating at different
rates.
Loopback Data Input for 10 Gbits/s CML.
Use this input for
system loopback data.
D14
F14
LBDP
LBDN
I
t
CML
Note:
This data input will scale when operating at different
rates.
FEC Rate (Active-Low).
Selects between two operating rate
ranges within the OC-192/STM-64 rate of 9.9532 GHz and
the FEC rate of 10.7092 GHz.
0 = Will extend the operating range out to the FEC rate of
10.7092 GHz.
1 or no connection = OC-192/STM-64 rate of 9.9532 GHz to
the Ethernet rate of 10.3 GHz.
A3
FECN
I
u
CMOS
Note:
An input and output SONET/SDH clock and data rates
will scale when operating at different rates.
Enable LBDP/N Inputs (Active-Low).
Selects LBDP/N as
data source rather than primary data input.
0 = Select LBDP/N.
1 or no connection = Select DATAP/N.
Resistor Reference VCO.
VCO bias reference resistor.
Connect a 1.2 k
resistor to V
CCA
.
Resistor Reference Charge Pump.
Charge pump bias
resistor. Connect a 1.2 k
resistor to V
CCA
.
Loss of Lock (Active-Low).
0 = Phase-locked loop (PLL) out of lock.
Loop Filter PLL.
Connect LFP and LFN to loop filter (see
Figure 5 on page 12).
C1
ENLBDN
I
u
CMOS
L14
RREFVCO
I
Analog
H14
RREFCP
I
Analog
B3
LCKLOSSN
O
CMOS
K14
J14
LFP
LFN
O
Analog
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