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參數(shù)資料
| 型號： | TSB14AA1 |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 電機及電子學工程師聯(lián)合會1394-1995。 3.3。 1-port.50/100Mbps。底板PHY |
| 文件頁數(shù)： | 15/35頁 |
| 文件大小： | 224K |
| 代理商： | TSB14AA1 |
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3
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3
Table 3-2. Base Register Field Description (Continued)
FIELD
SIZE
TYPE
DESCRIPTION
SMRST
1
R/W
State machine reset. When this bit is written to, TSB14AA1A first clears, then resets all
state machines in the PHY. This bit is self-clearing. The power-up state of this field is 0b.
SWHRST
1
R/W
Software initiate hardware reset. When this bit is set to 1, TSB14AA1A performs a reset
of the same nature as the reset caused by toggling the RESET pin on the device. This
clears all state machines and register settings to their power-on reset states. This bit is
self-clearing. The power-up state of this field is 0b.
LAST_ARB_WON_PRIORITY
4
R
Priority code of physical layer node that last won arbitration. This field contains the
priority used by the node that last won the arbitration process on the bus. It is only valid
when the E bit is 1. This field is supplied for system debug purposes. The power-up state
of this field is 0b.
DDLS
1
R/W
Drive data line state. When the M_TEST pin is asserted (high) and the ENDLS bit is set
to 1, the TSB14AA1A drives the state of the DDLS bit on the TDATA output pin of the
device. This mode of operation is for diagnostic testing only. It is not a valid 1394
operating mode and will not allow proper 1394 bus operation if connected to a 1394 bus.
The power-up state of this bit is 0b. The state of this bit is not affected by bus resets or
state machine resets. This bit is cleared upon HW or SWHRST reset.
DSLS
1
R/W
Drive strobe line state. When the M_TEST pin is asserted (high) and the ENDLS bit is
set to 1, the TSB14AA1A drives the state of the DSLS bit on the TSTRB output pin of the
device. This mode of operation is for diagnostic testing only. It is not a valid 1394
operation mode and will not allow proper 1394 bus operation if connected to a 1394 bus.
The power-up state of this bit is 0b. The state of this bit is not affected by bus resets or
state machine resets. This bit is cleared upon hardware or SWHRST reset.
ENDLS
1
R/W
Enable drive line state. When the M_TEST pin is asserted (high) and ENDLS is set to 1,
the TSB14AA1A drives the state of the DDLS bit on the TDATA output pin of the device.
It also drives the state of the DSLS bit on the TSTRB output pin of the device. This mode
of operation is for diagnostic testing only. It is not a valid 1394 operation mode and will
not allow proper 1394 bus operation if connected to a 1394 bus. The power-up state of
this bit is 0b. The state of this bit is not affected by bus resets or state machine resets.
This bit is cleared upon hardware or SWHRST reset.
TDATA
1
R
Transmitted data line state. When the E bit is 1, the line state read from this field is valid.
This bit reads 1 for a data line 1 (logical 1) being transmitted by the TSB14AA1A and 0
for a data line 0 (logical 0). The power-up state of this field is 0b. This bit is updated on a
best effort basis. TDATA is not required to be toggled with every change of the TDATA
output pin. It can be expected to be updated at least every 9 SCLKs, the length of the
register read LREQ.
TSTRB
1
R
Transmit strobe line state. When the E bit is 1, the line state read from this field is valid.
This bit reads 1 for a strobe line 1 (logical 1) being transmitted by the TSB14AA1A and 0
for a strobe line 0 (logical 0). The power-up state of this field is 0b. This bit is updated on a
best effort basis. TSTRB is not required to be toggled with every change of the TSTRB
output pin. It can be expected to be updated at least every 9 SCLKs, the length of the
register read LREQ.
TDOE
1
R
3-State output enable. When the E bit is 1, the state read from this field is valid. The
power-up state of this field is 0b. This bit is updated on a best effort basis. TDOE is not
required to be toggled with every change of the TDOE output pin. It can be expected to
be updated at least every 9 SCLKs, the length of the register read LREQ.
OCDOE
1
R
Open collector output enable. When the E bit is 1, the state read from this field is valid.
The power-up state of this field is 0b. This bit is updated on a best effort basis. OCDOE is
not required to be toggled with every change of the OCDOE output pin. It can be
expected to be updated at least every 9 SCLKs, the length of the register read LREQ.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
| TSB14AA1T | FPGA (Field-Programmable Gate Array) |
| TSB14C01MHV | IC APEX 20KE FPGA 160K 484-FBGA |
| TSB14C01HV | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB21LV03MHV | IC APEX 20KE FPGA 200K 484-FBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB14AA1A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3 V IEEE 1394-1995 BACKPLANE PHY |
| TSB14AA1AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3 V IEEE 1394-1995 BACKPLANE PHY |
| TSB14AA1AIPFB | 功能描述:1394 接口集成電路 IEEE139419953.3V1prt 50/100Mbps BkplnPHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1AIPFBG4 | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1APFB | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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