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參數資料
| 型號： | TSB14AA1 |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 電機及電子學工程師聯合會1394-1995。 3.3。 1-port.50/100Mbps。底板PHY |
| 文件頁數： | 26/35頁 |
| 文件大小： | 224K |
| 代理商： | TSB14AA1 |
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6
–
6
00
11
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
PHY Cti [0:1]
00
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
PHY D [0:7]
00
ZZ
ZZ
ZZ
01
01
10
10
10
10
00
00
ZZ
Link Cti [0:1]
ZZ
ZZ
00
00
D0
D1
D2
Dn
00
00
ZZ
Link D [0:7]
ZZ
Single Packet
ZZ
ZZ
ZZ
ZZ
00
11
00
ZZ
00
ZZ
ZZ
ZZ
PHY Cti [0:1]
ZZ
ZZ
ZZ
00
00
00
ZZ
00
ZZ
ZZ
ZZ
PHY D [0:7]
ZZ
10
10
01
00
ZZ
ZZ
ZZ
01
ZZ
01
10
10
Link Cti [0:1]
Dn-1
00
00
ZZ
ZZ
ZZ
00
ZZ
00
D0
D1
Link D [0:7]
Dn
Continued Packet
ZZ = High- Impedance State
D0 = > Dn = Packet Data
Figure 6
–
4. Transmit Timing
6.1.5
Receive
When data is received by the PHY from the serial bus, it transfers the data to the link for further processing. The PHY
asserts receive (see Table 6
–
1) on the CTL lines and asserts each D terminal high. The PHY indicates the start of
the packet by placing the speed code on the data bus. The PHY then proceeds with the transmission of the packet
to the link on the D lines while keeping the receive status on the CTL terminals. Once the packet has been completely
transferred, the PHY asserts idle on the CTL terminals, which completes the receive operation (see Figure 6
–
5).
NOTE:
The speed code is a PHY-link protocol and is not included in the CRC.
PHY
Ctl[0:1]
PHY
D[0:1]
00
10
10
10
10
10
10
00
00
00
11
11
SPD
D0
D1
Dn
00
00
NOTE A: SPD = Speed Code (for the backplane, this speed is fixed at D0, D1 = 00)
D0 to Dn = Packet data
Figure 6
–
5. Receive Timing
相關PDF資料 |
PDF描述 |
|---|---|
| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
| TSB14AA1T | FPGA (Field-Programmable Gate Array) |
| TSB14C01MHV | IC APEX 20KE FPGA 160K 484-FBGA |
| TSB14C01HV | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB21LV03MHV | IC APEX 20KE FPGA 200K 484-FBGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB14AA1A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3 V IEEE 1394-1995 BACKPLANE PHY |
| TSB14AA1AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3 V IEEE 1394-1995 BACKPLANE PHY |
| TSB14AA1AIPFB | 功能描述:1394 接口集成電路 IEEE139419953.3V1prt 50/100Mbps BkplnPHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1AIPFBG4 | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1APFB | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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