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參數資料
| 型號： | TSB14AA1 |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 電機及電子學工程師聯合會1394-1995。 3.3。 1-port.50/100Mbps。底板PHY |
| 文件頁數： | 20/35頁 |
| 文件大?。?/td> | 224K |
| 代理商： | TSB14AA1 |
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5
–
3
5.4
Using the EX_ID and EX_PRI Pins
During arbitration, each node that is arbitrating for the bus drives its priority code and then its arbitration number out
onto the bus. The most significant bit (MSB) of the priority field is transmitted first. The least significant bit (LSB) of
the priority field is followed by the MSB of the arbitration number. The lowest priority level (all zeroes) is reserved for
fair arbitration, and the highest priority level (all ones) is reserved for the identification of the cycle start packet. The
node with the highest priority (or if all priorities were zero, the highest node number) is the first to drive a 1 onto the
bus during arbitration. The node that sends the first 1 and reads it back wins the bus. In the TSB14AA1A, the priority
code and arbitration number can be set externally through the EX_PR and EX_ID pins. Upon hardware reset or
SWHRST, the 4-bit priority code and 6-bit physical_ID are reinitialized to the external pin values. However, unlike the
equivalent field in the cable environment, the priority and physical_ID in the backplane environment is writeable. The
priority code and physical_ID of each node can be reassigned to different values other than the external pin values
after the hardware reset or SWHRST.
5.5
Testability and Debug
The TSB14AA1A offers an extensive testability and debug function. The TSB14AA1A offers the following testability
enhancements:
Register 0000b may have all eight bits written to and read from for verification of
stuck at
bits or pins. Note
that bits 6 and 7 must be at a logical low (0) for correct normal operation.
Register 0010b contains the physical ID that last won the bus (sent the last packet). Note that after a robust
bus reset this field becomes all ones.
Register 0011b contains the currently captured values of the received data and received strobe pins on the
device for verification of the recent state of the 1394 bus. It also contains the state of the CLK_SEL0 and
CLK_SEL1 pins to verify correct setup of the TSB14AA1A.
Register 0101 contains the product identifier for the TSB14AA1A. This allows software to verify the revision
of the part that is installed in a system.
Register 0110b contains the priority of the last packet sent on the bus. Note that after a robust bus reset
this field becomes all ones.
Register 0111b may be used to verify the state of the pins TDATA, TSTRB, OCDOE, and TDOE by reading
the bits with the same name.
Register 0111b, in combination with register 0011b and the M-TEST pin, may be used to verify the
connectivity of the 14AA1A, the transceiver selected and the 1394 bus. Note that this test will break the 1394
bus by driving DC states on the bus. Normal operation is
not possible
when this test mode is invoked. The
connectivity test is performed as follows:
1.
Set the M_TEST pin to the HIGH state, to hardware enable this testing mode. To enable this, use a
jumper, dip switch, or higher layer GPIO.
Set the ENDLS bit to 1 via register write, to software enable the DC driving of the TDATA, TSTRB,
OCDOE, and TDOE pins.
With the M_TEST pin and ENDLS register bit set to 1, write 0 to DDLS.
Verify the TDATA bit reads 0 and RDATA bit reads 0
With the M_TEST pin and ENDLS register bit set to 1, write 1 to DDLS.
Verify the TDATA bit reads 1 and RDATA bit reads 1
With the M_TEST pin and ENDLS register bit set to 1, write 0 to DSLS.
Verify the TSTRB bit reads 0 and RSTRB bit reads 0
With the M_TEST pin and ENDLS register bit set to 1, write 1 to DSLS.
10. Verify the TSTRB bit reads 1 and RSTRB bit reads 1
11. To return to normal operation, set the M_TEST pin to 0 and set the ENDLS register bit to 0. The RDATA,
RSTRB, TDATA, TSTRB, TDOE, and OCDOE bits will still be operational since they are read-only bits.
2.
3.
4.
5.
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7.
8.
9.
相關PDF資料 |
PDF描述 |
|---|---|
| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
| TSB14AA1T | FPGA (Field-Programmable Gate Array) |
| TSB14C01MHV | IC APEX 20KE FPGA 160K 484-FBGA |
| TSB14C01HV | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB21LV03MHV | IC APEX 20KE FPGA 200K 484-FBGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB14AA1A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3 V IEEE 1394-1995 BACKPLANE PHY |
| TSB14AA1AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3 V IEEE 1394-1995 BACKPLANE PHY |
| TSB14AA1AIPFB | 功能描述:1394 接口集成電路 IEEE139419953.3V1prt 50/100Mbps BkplnPHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1AIPFBG4 | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1APFB | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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