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參數資料
| 型號： | TSB41LV03PFP |
| 英文描述： | IC APEX 20KE FPGA 600K 652-BGA |
| 中文描述： | 收發器 |
| 文件頁數： | 3/50頁 |
| 文件大小： | 662K |
| 代理商： | TSB41LV03PFP |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly
connected to the twisted-pair B terminals is coupled to ground through a parallel R-C network with
recommended values of 5 k
and 220 pF. The values of the external line-termination resistors are designed
to meet the standard specifications when connected in parallel with the internal receiver circuits. An external
resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal
operating currents. This current setting resistor has a value of 6.34 k
±
1%.
When the power supply of the TSB41AB3 is off while the twisted-pair cables are connected, the TSB41AB3
transmitter and receiver circuitry presents a high-impedance signal to the cable and does not load the TPBIAS
voltage at the other end of the cable.
When the TSB41AB3 is used without one or more of the ports brought out to a connector, the twisted-pair
terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and
TPB
–
terminals can be tied together and then pulled to ground, or the TPB+ and TPB
–
terminals can be
connected to the suggested termination network. The TPA+, TPA
–
, and TPBIAS terminals of an unused port
can be left unconnected. The TPBIAS terminal can be connected through a 1-
μ
F capacitor to ground or left
floating.
The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal
operation, it is recommended that the TESTM terminal be connected to V
DD
through a 1-k
resistor, and SE
be tied to ground through a 1-k
resistor, while SM is connected directly to ground.
Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID
packet and are tied high through a 1-k
resistor or hardwired low as a function of the equipment design. The
PC0
–
PC2 terminals are used to indicate the default power-class status for the node (the need for power from
the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON
terminal is used as an input to indicate that the node is a contender either for isochronous resource manager
(IRM) or for bus manager (BM).
The TSB41AB3 supports suspend/resume as defined in the IEEE 1394a-2000 specification. The suspend
mechanism allows pairs of directly-connected ports to be placed into a low-power conservation state
(suspended state) while maintaining a port-to-port connection between 1394 bus segments. While in the
suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the
suspended state is capable of detecting connection status changes and detecting incoming TPBias. When all
three ports of the TSB41AB3 are suspended, all circuits except the band-gap reference generator and bias
detection circuits are powered down resulting in significant power savings. For additional details of
suspend/resume operation refer to the IEEE 1394a-2000 specification. The use of suspend/resume is
recommended for new designs.
The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted
high), during reset (when the RESET input terminal is asserted low), when no active cable is connected to the
port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power down,
during reset, or when the port is disabled as commanded by the LLC.
The CNA (cable-not-active) terminal provides a high when there are no twisted-pair cable ports receiving
incoming bias (i.e., they are either disconnected or suspended) and can be used along with link power status
(LPS) to determine when to power down the TSB41AB3. The CNA output is not debounced. When the PD
terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports)
and a pulldown is activated on the RESET terminal so as to force a reset of the TSB41AB3 internal logic.
The LPS terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from
the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the
APPLICATION INFORMATION
section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize
the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of
the state of the LCtrl bit).
相關PDF資料 |
PDF描述 |
|---|---|
| TSB41AB2I | IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER |
| TSB41LV03AI | IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSC692E | 672-pin FineLine BGA |
| TSC695F | IC,FPGA,57120-CELL,CMOS,BGA,1020PIN,PLASTIC |
| TSC695FL | IC,FPGA,79040-CELL,CMOS,BGA,1020PIN,PLASTIC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB41LV03PFP WAF | 制造商:Texas Instruments 功能描述: |
| TSB41LV04A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER |
| TSB41LV04APFP | 功能描述:總線收發器 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| TSB41LV04APFPG4 | 功能描述:1394 接口集成電路 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41LV06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER |
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