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參數資料
型號: TSB41LV03PFP
英文描述: IC APEX 20KE FPGA 600K 652-BGA
中文描述: 收發器
文件頁數: 4/50頁
文件大小: 662K
代理商: TSB41LV03PFP
SLLS418G
JUNE 2000
REVISED JANUARY 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The LPS input is considered inactive if it remains low for more than 2.6
μ
s and is considered active otherwise.
When the TSB41AB3 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state
in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the
SYSCLK output remains active. If the LPS input remains low for more than 26
μ
s, the PHY-LLC interface is put
into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also
held in the disabled state during hardware reset. The TSB41AB3 continues the necessary repeater functions
required for normal network operation regardless of the state of the PHY
LLC interface. When the interface is
in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it
to normal operation.
When the PHY-LLC interface is in the low-power disabled state, the TSB41AB3 automatically enters a
low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB41AB3 disables its internal clock generators and also disables various voltage and current reference
circuits, depending on the state of the ports (some reference circuitry must remain active in order to detect new
cable connections, disconnections, or incoming TPBias, for example). The lowest power consumption (the
ultralow-power sleep
mode) is attained when all ports are either disconnected, or disabled with the port
s
interrupt enable bit cleared. The TSB41AB3 exits the low-power mode when the LPS input is asserted high or
when a port event occurs which requires that the TSB41AB3 become active in order to respond to the event
or to notify the LLC of the event (incoming bias is detected on a suspended port, a disconnection is detected
on a suspended port, a new connection is detected on a nondisabled port). The SYSCLK output becomes active
(and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is asserted high when
the TSB41AB3 is in the low-power mode.
The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the
C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when
the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is
inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet
addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the
C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also
deasserts the C/LKON output when a bus reset occurs unless a PHY interrupt condition exists which otherwise
causes C/LKON to be active.
The TSB41AB3 is characterized for operation from 0
°
C to 70
°
C. The TSB41AB3-EP is characterized for
operation from
40
°
C to 85
°
C.
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相關代理商/技術參數
參數描述
TSB41LV03PFP WAF 制造商:Texas Instruments 功能描述:
TSB41LV04A 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER
TSB41LV04APFP 功能描述:總線收發器 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
TSB41LV04APFPG4 功能描述:1394 接口集成電路 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB41LV06 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER
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