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參數(shù)資料
| 型號： | TSB41LV03PFP |
| 英文描述： | IC APEX 20KE FPGA 600K 652-BGA |
| 中文描述： | 收發(fā)器 |
| 文件頁數(shù)： | 34/50頁 |
| 文件大小： | 662K |
| 代理商： | TSB41LV03PFP |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
34
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
LLC service request (continued)
The 3-bit request speed field used in bus requests is shown in Table 15.
Table 15. Bus Request Speed Encoding
LR4-LR5
DATA RATE
000
S100
010
S200
100
S400
All others
Invalid
NOTE:
The TSB41AB3 accepts a bus request with an invalid speed code and process the bus request
normally. However, during packet transmission for such a request, the TSB41AB3 ignores any data
presented by the LLC and transmits a null packet.
For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 16.
Table 16. Read Register Request
BIT(s)
NAME
DESCRIPTION
0
Start bit
Indicates the beginning of the transfer (always 1)
1-3
Request type
A 100 indicating this is a read register request
4-7
Address
Identifies the address of the PHY register to be read
8
Stop bit
Indicates the end of the transfer (always 0)
For a write register request the length of the LREQ bit stream is 17 bits as shown in Table 17.
Table 17. Write Register Request
BIT(s)
NAME
DESCRIPTION
0
Start bit
Indicates the beginning of the transfer (always 1)
1-3
Request type
A 101 indicating this is a write register request
4-7
Address
Identifies the address of the PHY register to be written to
8-15
Data
Gives the data that is to be written to the specified register address
16
Stop bit
Indicates the end of the transfer (always 0)
For an acceleration control request the Length of the LREQ data stream is 6 bits as shown in Table 18.
Table 18. Acceleration Control Request
BIT(s)
NAME
DESCRIPTION
0
Start bit
Indicates the beginning of the transfer (always 1)
1-3
Request type
A 110 indicating this is an acceleration control request
4
Control
Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0
5
Stop bIt
Indicates the end of the transfer (always 0)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB41LV03PFP WAF | 制造商:Texas Instruments 功能描述: |
| TSB41LV04A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER |
| TSB41LV04APFP | 功能描述:總線收發(fā)器 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| TSB41LV04APFPG4 | 功能描述:1394 接口集成電路 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41LV06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER |
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