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參數資料
| 型號： | TSB41LV03PFP |
| 英文描述： | IC APEX 20KE FPGA 600K 652-BGA |
| 中文描述： | 收發(fā)器 |
| 文件頁數： | 38/50頁 |
| 文件大小： | 662K |
| 代理商： | TSB41LV03PFP |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
38
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
receive (continued)
The sequence of events for a normal packet reception is as follows:
1
a.
Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL
lines. Normally, the interface is idle when receive is asserted. However, the receive operation may
interrupt a status transfer operation that is in progress so that the CTL lines may change from status
to receive without an intervening idle.
Data-on indication. The PHY may assert the data-on indication code on the D lines for one or more
cycles preceding the speed-code.
Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D
lines for one cycle immediately preceding packet data. The link decodes the speed code on the first
receive cycle for which the D lines are not the data-on code. If the speed code is invalid, or indicates
a speed higher that that which the link is capable of handling, the link should ignore the subsequent data.
Receive data. Following the data-on indication (if any) and the speed-code, the PHY asserts packet
data on the D lines with receive on the CTL lines for the remainder of the receive operation.
b.
c.
d.
e.
Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL
lines. The PHY asserts at least one cycle of idle following a receive operation.
00
00
10
XX
(a)
(b)
(c)
FF (Data-On)
D0
–
D7
CTL0, CTL1
SYSCLK
00
01
Figure 19. Null Packet Reception Timing
The sequence of events for a null packet reception is as follows:
1
a.
Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL
lines. Normally, the interface is idle when receive is asserted. However, the receive operation may
interrupt a status transfer operation that is in progress so that the CTL lines may change from status
to receive without an intervening idle.
b.
Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.
c.
Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL
lines. The PHY asserts at least one cycle of idle following a receive operation.
Table 20. Receive Speed Codes
D0
–
D7
00XX XXXX
0100 XXXX
0101 0000
1YYY YYYY
DATA RATE
S100
S200
S400
data-on indication
NOTE: X = Output as 0 by PHY, ignored by LLC.
Y = Output as 1 by PHY, ignored by LLC.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB41LV03PFP WAF | 制造商:Texas Instruments 功能描述: |
| TSB41LV04A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER |
| TSB41LV04APFP | 功能描述:總線收發(fā)器 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| TSB41LV04APFPG4 | 功能描述:1394 接口集成電路 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41LV06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER |
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