- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382686 > TSB41LV03PFP IC APEX 20KE FPGA 600K 652-BGA PDF資料下載
參數(shù)資料
| 型號： | TSB41LV03PFP |
| 英文描述： | IC APEX 20KE FPGA 600K 652-BGA |
| 中文描述： | 收發(fā)器 |
| 文件頁數(shù)： | 40/50頁 |
| 文件大小： | 662K |
| 代理商： | TSB41LV03PFP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁
SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
40
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
transmit (continued)
00
00
00
00
10
(f)
(g)
(e)
(d)
(c)
(b)
(a)
01
00
00
00
00
00
11
dn
d0, d1, . . .
Link Controls CTL and D
PHY High-Impedance CTL and D Outputs
D0
–
D7
CTL0, CTL1
SYSCLK
NOTE A: SPD = Speed code (see Table 20), d0
–
dn = Packet data
00
01
00
SPD
Figure 20. Normal Packet Transmission Timing
The sequence of events for a normal packet transmission is as follows:
1
a.
Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over
control of the interface to the link so that the link may transmit a packet. The PHY releases control of
the interface (i.e., it places its CTL and D outputs in a high-impedance state) following the idle cycle.
b.
Optional idle cycle. The link may assert at most one idle cycle preceding assertion of either hold or
transmit. This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit.
c.
Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of transmit. These
hold cycle(s) are optional; the link is not required to assert hold preceding transmit.
d.
Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along
with the data on the D lines.
e.
Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle
on the CTL lines. The link asserts hold to indicate that the PHY is to retain control of the serial bus in
order to transmit a concatenated packet. The link asserts idle to indicate that packet transmission is
complete and the PHY may release the serial bus. The link then asserts idle for one more cycle following
this cycle of hold or idle before releasing the interface and returning control to the PHY.
f.
Concatenated packet speed-code. If multispeed concatenation is enabled in the PHY, the link asserts
a speed code on the D lines when it asserts hold to terminate packet transmission. This speed code
indicates the transmission speed for the concatenated packet that is to follow. The encoding for this
concatenated packet speed-code is the same as the encoding for the received packet speed code (see
Table 20). The link may not concatenate an S100 packet onto any higher-speed packet.
g.
After regaining control of the interface, the PHY asserts at least one cycle of idle before any subsequent
status transfer, receive operation, or transmit operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB41AB2I | IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER |
| TSB41LV03AI | IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSC692E | 672-pin FineLine BGA |
| TSC695F | IC,FPGA,57120-CELL,CMOS,BGA,1020PIN,PLASTIC |
| TSC695FL | IC,FPGA,79040-CELL,CMOS,BGA,1020PIN,PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB41LV03PFP WAF | 制造商:Texas Instruments 功能描述: |
| TSB41LV04A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER |
| TSB41LV04APFP | 功能描述:總線收發(fā)器 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| TSB41LV04APFPG4 | 功能描述:1394 接口集成電路 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41LV06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。