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參數(shù)資料
型號(hào)： TVP7002PZPR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： GREEN, PLASTIC, HTQFP-100
文件頁(yè)數(shù)： 24/57頁(yè)
文件大小： 517K
代理商： TVP7002PZPR
SLES206B
– MAY 2007 – REVISED MAY 2011
Red Fine Offset MSBs
Subaddress
0Dh
Default (80h)
7
6
5
4
3
2
1
0
Red Fine Offset [9:2]
Red Fine Offset [9:2]: 8 MSBs of 10-bit fine digital offset (brightness) for Red channel (applied after ADC). Corresponding two LSBs located
at register 1Dh. Offset binary value.
The default setting of 80h places the bottom-level (RGB) clamped output blank levels at 0 and mid-level clamped (PbPr) output blank levels
at 512.
FFh = Maximum fine offset
81h = 1 LSB
80h = 0 (default)
7Fh =
–1 LSB
00h = Minimum fine offset
Sync Control 1
Subaddress
0Eh
Default (5Bh)
7
6
5
4
3
2
1
0
HSPO
HSIP
HSOP
AHSO
AHSS
VSOP
AVSO
AVSS
HSPO: HSYNC polarity override
0 = Polarity determined by chip (default)
1 = Polarity set by bit 6 in register 0Eh (not recommended)
HSIP: HSYNC input polarity
0 = Indicates input HSYNC polarity active low
1 = Indicates input HSYNC polarity active high (default)
HSOP: HSYNC output polarity
0 = Active-low HSYNC output (default)
1 = Active-high HSYNC output
NOTE: HSOP has no effect in raw sync bypass mode. See register 36h.
AHSO: Active HSYNC override
0 = Active HSYNC is automatically selected by TVP7002. If selected, SOG and HSYNC inputs both have active inputs,
HSYNC is selected as the active sync source. The selected active HSYNC is provided via the AHS status bit (bit 6 of
register 14h).
1 = Active HSYNC is manually selected via the AHSS control bit (bit 3 of register 0Eh). (default)
NOTE: Automatic sync selection should be enabled only for 5-wire PC graphics inputs.
AHSS: Active HSYNC select. The indicated HSYNC is used only if the AHSO control bit (bit 4) is set to 1 or if activity is detected on both
the selected HSYNC input and the selected SOG input (bits 1, 7 = 1 in register 14h).
0 = Active HSYNC is derived from the selected HSYNC input.
1 = Active HSYNC is derived from the selected SOG input (default).
VSOP: VSYNC output polarity
0 = Active-low VSYNC output (default)
1 = Active-high VSYNC output
AVSO: Active VSYNC override
0 = Active VSYNC is automatically selected by TVP7002. If selected, SOG and VSYNC inputs both have active inputs,
VSYNC is selected as the active sync source. The selected active VSYNC is provided via the AVS status bit (bit 3 of
register 14h).
1 = Active VSYNC is manually selected via the AVSS control bit (bit 0 of register 0Eh) (default).
NOTE: Automatic sync selection should be enabled only for 5-wire PC graphics inputs.
AVSS: Active VSYNC select. This bit is effective when the AVSO control bit (bit 1) is set to 1.
0 = Active VSYNC is derived from the selected VSYNC input.
1 = Active VSYNC is derived from the Sync separated VSYNC (default).
30
Copyright
2007–2011, Texas Instruments Incorporated
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