- 您現在的位置：買賣IC網 > PDF目錄98307 > TVP7002PZPR (TEXAS INSTRUMENTS INC) SPECIALTY CONSUMER CIRCUIT, PQFP100 PDF資料下載
參數資料
| 型號： | TVP7002PZPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數： | 31/57頁 |
| 文件大小： | 517K |
| 代理商： | TVP7002PZPR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁
SLES206B
– MAY 2007 – REVISED MAY 2011
Input Mux Select 2
Subaddress
1Ah
Default (C2h)
7
6
5
4
3
2
1
0
SOG LPF SEL [1:0]
CLP LPF SEL [1:0]
CLK SEL
VS SEL
PCLK SEL
HS SEL
SOG LPF SEL [1:0]: SOG low-pass filter selection. The SOG low-pass filter can be used to attenuate glitches present on
the SOG input. Excessive filtering can lead to sync detection issues and increased sample clock jitter.
00 = 2.5-MHz low-pass filter
01 = 10-MHz low-pass filter
10 = 33-MHz low-pass filter
11 = Low-pass filter bypass (default)
CLP LPF SEL [1:0]: Coarse clamp low-pass filter selection. This filter effects the operation of all enabled coarse clamps which is generally
the SOG coarse clamp only.
00 = 4.8-MHz low-pass filter (default). Suitable for HDTV and graphics formats.
01 = 0.5-MHz low-pass filter. Suitable for SDTV formats.
10 = 1.7-MHz low-pass filter
11 = Reserved
CLK SEL: Clock reference select for Sync Processing block. The internal reference clock is typically 6.5 MHz, but it should not be
considered a precise clock. An external 27-MHz reference clock is therefore recommended for accurate mode detection. NOTE: The I2C
interface, Sync Separator, and activity detection circuitry always uses the internal clock reference.
0 = Internal clock reference (default)
1 = External clock reference (EXT_CLK)
NOTE: The external clock input can also be selected as the sample clock for the ADCs (see bit 1).
VS SEL: VSYNC input select
0 = VSYNC_A input selected (default)
1 = VSYNC_B input selected
PCLK SEL: Pixel clock selection. When the external clock input (pin 80) is selected as the ADC sample clock, the external clamp pulse
(pin 76) should also be selected (Bit 7 of subaddress 0Fh).
0 = ADC samples data using external clock input (pin 80)
1 = ADC samples data using H-PLL generated clock (default)
NOTE: The external clock input can also be selected as the reference clock for the Sync Processing block (see bit 3).
HS SEL: HSYNC input select
0 = HSYNC_A input selected (default)
1 = HSYNC_B input selected
NOTE: See the Sync Control register at subaddress 0Eh.
Copyright
2007–2011, Texas Instruments Incorporated
37
相關PDF資料 |
PDF描述 |
|---|---|
| TVP7002PZP | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| TWL1101PFB | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| TWL1101PFBR | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| TWL1102PBS | SPECIALTY CONSUMER CIRCUIT, PQFP32 |
| TWL1102PBSR | SPECIALTY CONSUMER CIRCUIT, PQFP32 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TVP9000MZDSR | 制造商:Texas Instruments 功能描述: |
| TVP9000ZDS | 制造商:Texas Instruments 功能描述: |
| TVP9000ZDSR | 制造商:Texas Instruments 功能描述: |
| TVP9001ZDS | 制造商:Texas Instruments 功能描述: |
| TVP9001ZDSR | 制造商:Texas Instruments 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。