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參數資料
| 型號： | TVP7002PZPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數： | 42/57頁 |
| 文件大小： | 517K |
| 代理商： | TVP7002PZPR |
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SLES206B
– MAY 2007 – REVISED MAY 2011
Lines Per Frame Status
Subaddress
37h
–38h
Read only
Subaddress
7
6
5
4
3
2
1
0
37h
Lines per Frame [7:0]
38h
Reserved
mac detect
P/I detect
Reserved
Lines per Frame [11:8]
mac detect: Macrovision pseudo-sync detection status
0 = Macrovision not detected
1 = Macrovision detected
P/I detect: Progressive/interlaced video detection status. Not dependent on the H-PLL being locked.
0 = Interlaced video detected
1 = Progressive video detected
Lines per Frame [11:0]: Number of lines per frame.
The lines per frame value may be used along with the clocks per line value (subaddresses 39h
–3Ah) to determine the vertical frequency
(fV) of the video input.
fV = clock reference frequency / clocks per line / lines per frame
NOTE: The Lines per Frame counter is not dependent on the H-PLL being locked.
Table 16. Expected Status Read-Back When Using a 27-MHz REFCLK
Clocks Per
Lines per
HSYNC
Format
I/P Bit
HS POL
Line
frame
Width
480i60Hz
1716
525
126
0
1
480p60Hz
858
525
63
1
576i50Hz
1728
625
126
0
1
576p50Hz
864
625
63
1
720p60Hz
600
750
14
1
1080i60Hz
800
1125
16
0
1
1080p60Hz
400
1125
8
1
XGA60Hz
558
806
56
1
0
XGA75Hz
449
800
32
1
Clocks Per Line Status
Subaddress
39h
–3Ah
Read only
Subaddress
7
6
5
4
3
2
1
0
39h
Clocks per Line [7:0]
3Ah
Reserved
Clocks per Line [11:8]
Clocks per Line [11:0]: Number of clock cycles per line. The value written to this register represents the length of the longest line per frame.
A known timing reference based on either the internal clock reference (~6.5 MHz) or an external clock reference input (EXT_CLK) of up to
27 MHz may be selected using subaddress 1Ah.
The clocks per line value may be used to determine the horizontal frequency (fH) of the video input.
fH = clock reference frequency / clocks per line
NOTE: The Clocks per Line counter is not dependent on the H-PLL being locked.
HSYNC Width
Subaddress
3Bh
Read only
7
6
5
4
3
2
1
0
HSYNC width [7:0]
HSYNC width [7:0]: Number of clock cycles between the leading and trailing edges of the HSYNC input. A known timing reference based
on either the internal clock reference (~6.5 MHz) or an external clock reference input (EXT_CLK) of up to 27 MHz may be selected using
subaddress 1Ah.
NOTE: The HSYNC width counter is not dependent on the H-PLL being locked.
Copyright
2007–2011, Texas Instruments Incorporated
47
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