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參數資料
| 型號： | TVP7002PZPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數： | 9/57頁 |
| 文件大小： | 517K |
| 代理商： | TVP7002PZPR |
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SLES206B
– MAY 2007 – REVISED MAY 2011
If activity is not detected on either the HSYNC input or the VSYNC input, the host processor should assume that
the PC graphics input is a standard 3-wire interface. With AHSO and AVSO set for automatic selection and no
signals present at the HSYNC and VSYNC input pins, the TVP7002 will automatically select the SOG input as
the sync source.
Table 5. Sync Activity Detection
VSYNC INPUT
HSYNC INPUT
PC GRAPHICS
ACTIVITY DETECT
INPUT TYPE
1
5 wire (default)
0
1
4 wire
0
3 wire
The activity detection status for the VSYNC and HSYNC inputs is written to the I2C status register at subaddress
14h.
NOTE
Pin 13 of a standard 15-pin VGA video connector can be either a horizontal sync
(HSYNC) or a composite sync (CSYNC). Automatic HSYNC polarity detection is
recommended (Reg 0Eh HSPO=0) for all sync types.
NOTE
For component video inputs, the active HSYNC and VSYNC should always be derived
from the selected SOG input. This can most easily be ensured by setting the AHSO,
AVSO, AHSS and AVSS bit fields in register 0Eh to logic 1.
NOTE
For proper operation when separate HSYNC and VSYNC inputs are used, the leading
edge of VSYNC must not be precisely aligned with the leading edge of HSYNC. A simple
RC delay circuit will provide adequate delay in most applications.
Copyright
2007–2011, Texas Instruments Incorporated
17
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