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參數(shù)資料
| 型號： | TVP7002PZPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 41/57頁 |
| 文件大?。?/td> | 517K |
| 代理商： | TVP7002PZPR |
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SLES206B
– MAY 2007 – REVISED MAY 2011
Macrovision Stripper Width
Subaddress
34h
Default (03h)
7
6
5
4
3
2
1
0
stripper width [7:0]
When the MAC_EN bit in Reg 22h is set to 1, this setting creates a stripper window around HSYNC for masking Macrovision pseudo-syncs
or glitches that could affect PLL lock. The actual stripper width is determined from the stripper width [7:0] setting and can be approximated
by 2 x stripper width [7:0] x REFCLK period. If set too low, stripper width [7:0] can adversely affect fine clamp and ALC placement. Reg 3Bh
can be used for read-back of the HSYNC width for automation of this setup . To ensure proper operation of fine clamp and ALC, a minimum
stripper width[7:0] setting of Reg 3Bh (HSYNC wdith) + Reg 3Dh (Line Length Tolerance) can be used. The maximum width is determined
from the start of the Macrovision pseudo-syncs and the video input line length. Stripper width [7:0] settings exceeding one half of the input
video line length cannot be used. Recommended settings for the more common formats are shown below for a Line Length Tolerance
setting of 3. Stripper width [7:0] has no effect, when the MAC_EN bit in Reg 22h is set to 0.
Table 15. Recommended Stripper Width Settings
VIDEO STANDARD
INTERNAL REFCLK USED
EXTERNAL 27-MHZ REFCLK USED
480i and 576i
24h
83h
480p and 576p
12h
43h
720p
07h
12h
1080i
07h
13h
1080p
03h
09h
VSYNC Alignment
Subaddress
35h
Default (10h)
7
6
5
4
3
2
1
0
VS-HS Align [7:0]
VS-HS Align [7:0]: Specifies the number of pixels that the leading edge of the VSYNC output should be delayed or advanced relative to the
leading edge of the HSYNC output. The Field ID output is delayed by the same amount. Twos-complement number. This register has no
effect when either Sync bypass mode is enabled (see subaddresses 22h and 36h).
00h
–7Fh = VSYNC leading edge delayed relative to the HSYNC leading edge
FFh
–80h = VSYNC leading edge advanced relative to the HSYNC leading edge
Sync Bypass
Subaddress
36h
Default (00h)
7
6
5
4
3
2
1
0
Reserved
VS INV
HS INV
VS BP
HS BP
VS INV: VSYNC output polarity control. This bit only has an effect if the VSYNC bypass is asserted (bit 1 = 1).
0 = HSYNC output polarity matches input polarity (default)
1 = HSYNC output polarity inverted
HS INV: HSYNC output polarity control. This bit only has an effect if the HSYNC bypass is asserted (bit 0 = 1).
0 = HSYNC output polarity matches input polarity (default)
1 = HSYNC output polarity inverted
VS BP: VSYNC bypass. This bit enables bypassing the Sync processing block in order to output a raw unprocessed VSYNC.
0 = Normal operation (default)
1 = VSYNC bypass mode. Can be used with PC graphics using discrete syncs.
HS BP: HSYNC bypass. This bit enables bypassing the Sync processing block in order to output a raw unprocessed HSYNC.
0 = Normal operation (default)
1 = HSYNC bypass mode. Can be used for sync detection but is not recommended for normal operation
NOTE: See register 14h for input sync polarity detect.
46
Copyright
2007–2011, Texas Instruments Incorporated
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