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參數資料
| 型號： | AD7707 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| 中文描述： | 3 V / 5號第五，1毫瓦3 -10 V輸入范圍通道16位Σ-Δ模數轉換器 |
| 文件頁數： | 22/40頁 |
| 文件大小： | 316K |
| 代理商： | AD7707 |
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REV. A
AD7707
–22–
Filter Characteristics
The AD7707’s digital filter is a low-pass filter with a (sinx/x)
3
response (also called sinc
3
). The transfer function for this filter
is described in the z-domain by:
1
H( )
N
Z
Z
N
–
–
=
×
1
1
1
3
and in the frequency domain by:
H( )
N
SIN N
f f
/
SIN
f f
/
S
S
(
)
(
)
=
×
×
π
×
×
1
3
π
where
N
is the ratio of the modulator rate to the output rate.
Phase Response:
∠
=
×
H
N
f f
/
Rad
–
(
– )
2
3
π
S
Figure 14 shows the filter frequency response for a cutoff fre-
quency of 2.62Hz, which corresponds to a first filter notch
frequency of 10Hz. The plot is shown from dc to 65 Hz. This
response is repeated at either side of the digital filter’s sample
frequency and at either side of multiples of the filter’s sample
frequency.
The response of the filter is similar to that of an averaging filter,
but with a sharper roll-off. The output rate for the digital filter
corresponds with the positioning of the first notch of the filter’s
frequency response. Thus, for the plot of Figure 14 where the
output rate is 10 Hz, the first notch of the filter is at 10 Hz. The
notches of this (sinx/x)
3
filter are repeated at multiples of the
first notch. The filter provides attenuation of better than 100dB
at these notches.
FREQUENCY – Hz
0
–140
–240
0
G
10
20
30
40
50
60
–20
–160
–180
–60
–100
–40
–80
–200
–220
–120
Figure 14. Frequency Response of AD7707 Filter
Simultaneous 50 Hz and 60 Hz rejection is obtained by placing
the first notch at 10 Hz. Operating with an update rate of 10 Hz
places notches at both 50 Hz and 60 Hz giving better than 100dB
rejection at these frequencies.
The cutoff frequency of the digital filter is determined by the
value loaded to bits FS0 to FS2 in the CLOCK Register. Pro-
gramming a different cutoff frequency via FS0 and FS1 does not
alter the profile of the filter response, it changes the frequency of
the notches. The output update of the part and the frequency of
the first notch correspond.
Since the AD7707 contains this on-chip, low-pass filtering, a
settling time is associated with step function inputs and data on
the output will be invalid after a step change until the settling
time has elapsed. The settling time depends upon the output
rate chosen for the filter. The settling time of the filter to a full-
scale step input can be up to four times the output data period.
For a synchronized step input (using the FSYNC function), the
settling time is three times the output data period.
Post-Filtering
The on-chip modulator provides samples at a 19.2 kHz output
rate with f
CLKIN
at 2.4576MHz. The on-chip digital filter deci-
mates these samples to provide data at an output rate that corre-
sponds to the programmed output rate of the filter. Since the
output data rate is higher than the Nyquist criterion, the output
rate for a given bandwidth will satisfy most application require-
ments. There may, however, be some applications which require
a higher data rate for a given bandwidth and noise performance.
Applications that need this higher data rate will require some
post-filtering following the digital filter of the AD7707.
For example, if the required bandwidth is 7.86Hz, but the
required update rate is 100 Hz, the data can be taken from the
AD7707 at the 100 Hz rate giving a –3 dB bandwidth of 26.2 Hz.
Post-filtering can be applied to this to reduce the bandwidth and
output noise, to the 7.86 Hz bandwidth level, while maintaining
an output rate of 100 Hz.
Post-filtering can also be used to reduce the output noise from
the device for bandwidths below 2.62 Hz. At a gain of 128 and a
bandwidth of 2.62 Hz, the output rms noise is 450 nV. This is
essentially device noise or white noise and since the input is
chopped, the noise has a primarily flat frequency response. By
reducing the bandwidth below 2.62 Hz, the noise in the result-
ant passband can be reduced. A reduction in bandwidth by a
factor of 2 results in a reduction of approximately 1.25 in the
output rms noise. This additional filtering will result in a longer
settling-time.
Analog Filtering
The digital filter does not provide any rejection at integer mul-
tiples of the modulator sample frequency, as outlined earlier.
However, due to the AD7707’s high oversampling ratio, these
bands occupy only a small fraction of the spectrum and most
broadband noise is filtered. This means that the analog filtering
requirements in front of the AD7707 are considerably reduced
versus a conventional converter with no on-chip filtering. In
addition, because the part’s common-mode rejection perfor-
mance of 100 dB extends out to several kHz, common-mode
noise in this frequency range will be substantially reduced.
Depending on the application, however, it may be necessary to
provide attenuation prior to the AD7707 in order to eliminate
unwanted frequencies from these bands which the digital filter
will pass. It may also be necessary in some applications to
provide analog filtering in front of the AD7707 to ensure that
differential noise signals outside the band of interest do not
saturate the analog modulator.
If passive components are placed in front of the AD7707 in
unbuffered mode, care must be taken to ensure that the source
impedance is low enough not to introduce gain errors in the sys-
tem. This significantly limits the amount of passive antialiasing
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