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參數資料
| 型號： | AD7707 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| 中文描述： | 3 V / 5號第五，1毫瓦3 -10 V輸入范圍通道16位Σ-Δ模數轉換器 |
| 文件頁數： | 8/40頁 |
| 文件大小： | 316K |
| 代理商： | AD7707 |
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REV. A
AD7707
–8–
Pin No.
Mnemonic
Function
14
REF IN(–)
Reference Input. Negative input of the differential reference input to the AD7707. The
REFIN(–) can lie anywhere between AV
DD
and AGND provided REFIN(+) is greater than
REFIN(–).
Analog Ground. Ground reference point for the AD7707’s internal analog circuitry.
Logic Output. A logic low on this output indicates that a new output word is available from the
AD7707 data register. The
DRDY
pin will return high upon completion of a read operation of a
full output word. If no data read has taken place between output updates, the
DRDY
line will
return high for 500
×
t
CLKIN
cycles prior to the next output update. While
DRDY
is high, a read
operation should neither be attempted nor in progress to avoid reading from the data register as
it is being updated. The
DRDY
line will return low again when the update has taken place.
DRDY
is also used to indicate when the AD7707 has completed its on-chip calibration
sequence.
Serial Data Output with serial data being read from the output shift register on the part. This
output shift register can contain information from the setup register, communications register,
clock register or data register, depending on the register selection bits of the Communications
Register.
Serial Data Input with serial data being written to the input shift register on the part. Data from
this input shift register is transferred to the setup register, clock register or communications
register, depending, on the register selection bits of the Communications Register.
Digital Supply Voltage, +2.7 V to +5.25 V operation.
Ground reference point for the AD7707’s internal digital circuitry.
15
16
AGND
DRDY
17
DOUT
18
DIN
19
20
DV
DD
DGND
OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (5 V OPERATION)
Table I shows the AD7707 output rms noise and peak-to-peak resolution in unbuffered mode for the selectable notch and –3dB
frequencies for the part, as selected by FS0, FS1 and FS2 of the Clock Register. The numbers given are for the bipolar input ranges
with a V
REF
of +2.5V and AV
DD
= 5 V. These numbers are typical and are generated at an analog input voltage of 0V. Table II
shows the rms noise and peak-to-peak resolution when operating in unbuffered mode.
It is important to note that the peak-to-peak num-
bers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-to-peak noise.
The
numbers given are for bipolar input ranges with a V
REF
of +2.5 V. These numbers are typical and are rounded to the nearest LSB.
The numbers apply for the CLK DIV bit of the Clock Register set to 0. The output noise comes from two sources. The first is the
electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog
input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of fre-
quency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise
source. The numbers in the tables are given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the
same as the bipolar range but the peak-to-peak resolution is now based on half the signal range which effectively means losing 1 bit of
resolution.
Table I. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +5 V
AIN1 and AIN2 Unbuffered Mode Only
Filter First
Notch and O/P
Data Rate
Typical Output RMS Noise in
m
V
Gain of
Gain of
2
4
(Peak-to-Peak Resolution in Bits)
Gain of
Gain of
16
32
–3dB
Frequency
Gain of
1
Gain of
8
Gain of
64
Gain of
128
MCLK IN = 2.4576 MHz
10Hz
50Hz
60Hz
250Hz
500Hz
2.62Hz
13.1Hz
15.72Hz
65.5Hz
131Hz
1.2 (16)
3.6 (16)
4.7 (16)
95 (13)
600 (10.5) 316 (10.5) 138 (10.5)
0.7 (16)
2.1 (16)
2.6 (16)
65 (13)
0.7 (16)
1.25 (16)
1.5 (16)
23.4 (13)
0.54 (16)
0.89 (16)
0.94 (16)
11.6 (13)
71 (10.5)
0.28 (16)
0.62 (16)
0.73 (16)
6.5 (13)
38 (10.5)
0.28 (16)
0.60 (15.5) 0.56 (14.5) 0.56 (13.5)
0.68 (15.5) 0.66 (14.5) 0.63 (13.5)
3.4 (13)
2.1 (12.5)
18 (10.5)
10 (10)
0.28 (15.5) 0.27 (14.5)
1.5 (12)
5.7 (10)
MCLK IN = 1 MHz
4.05Hz
20Hz
25Hz
100Hz
200Hz
1.06Hz
5.24Hz
6.55Hz
26.2Hz
52.5Hz
1.19 (16)
3.68 (16)
4.78 (16)
100 (13)
543 (10.5) 318 (10.5) 132 (10.5)
0.69 (16)
2.18 (16)
2.66 (16)
50.1 (13)
0.71 (16)
1.19 (16)
1.51 (16)
23.5 (13)
0.63 (16)
0.94 (16)
1.07 (16)
11.9 (13)
68.1 (10.5) 33.1 (10.5) 17.6 (10.5) 9.26 (10.5) 6.13 (10)
0.27 (16)
0.6 (16)
0.7 (16)
5.83 (13)
0.27 (16)
0.6 (15.5)
0.67 (15.5) 0.66 (14.5) 0.65 (13.5)
3.64 (13)
2.16 (12.5) 1.5 (12)
0.26 (15.5) 0.24 (15)
0.56 (14.5) 0.56 (13.5)
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