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參數資料
| 型號： | AD7707 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| 中文描述： | 3 V / 5號第五，1毫瓦3 -10 V輸入范圍通道16位Σ-Δ模數轉換器 |
| 文件頁數： | 23/40頁 |
| 文件大小： | 316K |
| 代理商： | AD7707 |
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REV. A
AD7707
–23–
filtering which can be provided in front of the AD7707 when it
is used in unbuffered mode. However, when the part is used in
buffered mode, large source impedances will simply result in a
small dc offset error (a 10 k
source resistance will cause an
offset error of less than 10
μ
V). Therefore, if the system requires
any significant source impedances to provide passive analog
filtering in front of the AD7707, it is recommended that the part
be operated in buffered mode.
CALIBRATION
The AD7707 provides a number of calibration options which
can be programmed via the MD1 and MD0 bits of the Setup
Register. The different calibration options are outlined in the
Setup Register and Calibration Sequences sections. A calibration
cycle may be initiated at any time by writing to these bits of the
Setup Register. Calibration on the AD7707 removes offset and
gain errors from the device. A calibration routine should be
initiated on the device whenever there is a change in the ambient
operating temperature or supply voltage. It should also be initi-
ated if there is a change in the selected gain, filter notch or bipo-
lar/unipolar input range.
The AD7707 offers self-calibration and system calibration facili-
ties. For full calibration to occur on the selected channel, the on-
chip microcontroller must record the modulator output for two
different input conditions. These are “zero-scale” and “full-
scale” points. These points are derived by performing a conver-
sion on the different input voltages provided to the input of the
modulator during calibration. As a result, the accuracy of the
calibration can only be as good as the noise level that it provides
in normal mode. The result of the “zero-scale” calibration con-
version is stored in the Zero-Scale Calibration Register while the
result of the “full-scale” calibration conversion is stored in the
Full-Scale Calibration Register. With these readings, the micro-
controller can calculate the offset and the gain slope for the
input-to-output transfer function of the converter.
Self-Calibration
A self-calibration is initiated on the AD7707 by writing the
appropriate values (0, 1) to the MD1 and MD0 bits of
the Setup Register. In the self-calibration mode with a unipolar
input range, the zero-scale point used in determining the calibra-
tion coefficients is with the inputs of the differential pair inter-
nally shorted on the part (i.e., AIN1 = LOCOM = Internal Bias
Voltage in the case of the AD7707. The PGA is set for the se-
lected gain (as per G1 and G0 bits in the Communications Reg-
ister) for this zero-scale calibration conversion. The full-scale
calibration conversion is performed at the selected gain on an
internally-generated voltage of V
REF
/Selected Gain.
The duration time for the calibration is 6
×
1/Output Rate. This
is made up of 3
×
1/Output Rate for the zero-scale calibration
and 3
×
1/Output Rate for the full-scale calibration. At this time
the MD1 and MD0 bits in the Setup Register return to 0, 0.
This gives the earliest indication that the calibration sequence is
complete. The
DRDY
line goes high when calibration is initi-
ated and does not return low until there is a valid new word in
the data register. The duration time from the calibration com-
mand being issued to
DRDY
going low is 9
×
1/Output Rate.
This is made up of 3
×
1/Output Rate for the zero-scale calibra-
tion, 3
×
1/Output Rate for the full-scale calibration, 3
×
1/Out-
put Rate for a conversion on the analog input and some overhead
to correctly set up the coefficients. If
DRDY
is low before (or
goes low during) the calibration command write to the Setup
Register, it may take up to one modulator cycle (MCLKIN/
128) before
DRDY
goes high to indicate that calibration is in
progress. Therefore,
DRDY
should be ignored for up to one
modulator cycle after the last bit is written to the Setup Register
in the calibration command.
For bipolar input ranges in the self-calibrating mode, the se-
quence is very similar to that just outlined. In this case, the two
points are exactly the same as above but, since the part is config-
ured for bipolar operation, the shorted inputs point is actually
midscale of the transfer function.
Errors due to resistor mismatch in the attenuator on the high
level input channel AIN3 are not removed by a self-calibration.
System Calibration
System calibration allows the AD7707 to compensate for system
gain and offset errors as well as its own internal errors. System
calibration performs the same slope factor calculations as self-
calibration, but uses voltage values presented by the system to
the AIN inputs for the zero- and full-scale points. Full system
calibration requires a two-step process, a ZS System Calibration
followed by an FS System Calibration.
For a full system calibration, the zero-scale point must be pre-
sented to the converter first. It must be applied to the converter
before the calibration step is initiated and remain stable until the
step is complete. Once the system zero-scale voltage has been
set up, a ZS System Calibration is then initiated by writing the
appropriate values (1, 0) to the MD1 and MD0 bits of the
Setup Register. The zero-scale system calibration is performed
at the selected gain. The duration of the calibration is 3
×
1/
Output Rate. At this time, the MD1 and MD0 bits in the Setup
Register return to 0, 0. This gives the earliest indication that the
calibration sequence is complete. The
DRDY
line goes high
when calibration is initiated and does not return low until there
is a valid new word in the data register. The duration time from
the calibration command being issued to
DRDY
going low is 4
×
1/Output Rate as the part performs a normal conversion on
the AIN voltage before
DRDY
goes low. If
DRDY
is low before
(or goes low during) the calibration command write to the Setup
Register, it may take up to one modulator cycle (MCLKIN/128)
before
DRDY
goes high to indicate that calibration is in progress.
Therefore,
DRDY
should be ignored for up to one modulator
cycle after the last bit is written to the Setup Register in the
calibration command.
After the zero-scale point is calibrated, the full-scale point is
applied to AIN and the second step of the calibration process is
initiated by again writing the appropriate values (1, 1) to MD1
and MD0. Again, the full-scale voltage must be set up before
the calibration is initiated and it must remain stable throughout
the calibration step. The full-scale system calibration is per-
formed at the selected gain. The duration of the calibration is
3
×
1/Output Rate. At this time, the MD1 and MD0 bits in the
Setup Register return to 0, 0. This gives the earliest indication
that the calibration sequence is complete. The
DRDY
line goes
high when calibration is initiated and does not return low until
there is a valid new word in the data register. The duration time
from the calibration command being issued to
DRDY
going low
is 4
×
1/Output Rate as the part performs a normal conversion
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| AD7707BR | 功能描述:IC ADC 16BIT 3CH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
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| AD7707BR-REEL7 | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 500sps 16-bit Serial 20-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.5KSPS 16BIT SERL 20SOIC W - Tape and Reel |
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| AD7707BRU-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 500sps 16-bit Serial 20-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.5KSPS 16BIT SERL 20TSSOP - Tape and Reel |
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