- 您現在的位置：買賣IC網 > PDF目錄373914 > AD7713SQ (ANALOG DEVICES INC) LC2MOS Loop-Powered Signal Conditioning ADC PDF資料下載
參數資料
| 型號： | AD7713SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Loop-Powered Signal Conditioning ADC |
| 中文描述： | 3-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件頁數： | 19/28頁 |
| 文件大小： | 516K |
| 代理商： | AD7713SQ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
2
–19–
REV. C
AD7713
output data register. It is reset high when the last bit of data
(either 16th bit or 24th bit) is read from the output register. If
data is not read from the output register, the
DRDY
line will
remain low. The output register will continue to be updated at
the output update rate but
DRDY
will not indicate this. A read
from the device in this circumstance will access the most recent
word in the output register. If a new data word becomes avail-
able to the output register while data is being read from the out-
put register,
DRDY
will not indicate this and the new data word
will be lost to the user.
DRDY
is not affected by reading from
the control register or the calibration registers.
Data can only be accessed from the output data register when
DRDY
is low. If
RFS
goes low with
DRDY
high, no data trans-
fer will take place.
DRDY
does not have any effect on reading
data from the control register or from the calibration registers.
Figure 10 shows a timing diagram for reading from the AD7713
in the self-clocking mode. This read operation shows a read
from the AD7713’s output data register. A read from the con-
trol register or calibration registers is similar, but in these cases
the
DRDY
line is not related to the read function. Depending
on the output update rate, it can go low at any stage in the con-
trol/calibration register read cycle without affecting the read and
its status should be ignored. A read operation from either the
control or calibration registers must always read 24 bits of data
from the respective register.
Figure 10 shows a read operation from the AD7713. For the
timing diagram shown, it is assumed that there is a pull-up resis-
tor on the SCLK output. With
DRDY
low, the
RFS
input is
brought low.
RFS
going low enables the serial clock of the
AD7713 and also places the MSB of the word on the serial data
line. All subsequent data bits are clocked out on a high to low
transition of the serial clock and are valid prior to the following
rising edge of this clock. The final active falling edge of SCLK
clocks out the LSB, and this LSB is valid prior to the final active
rising edge of SCLK. Coincident with the next falling edge of
SCLK,
DRDY
is reset high.
DRDY
going high turns off the
SCLK and the SDATA outputs. This means that the data hold
time for the LSB is slightly shorter than for all other bits.
DIGITAL INTERFACE
The AD7713’s serial communications port provides a flexible
arrangement to allow easy interfacing to industry-standard
microprocessors, microcontrollers and digital signal processors.
A serial read to the AD7713 can access data from the output
register, the control register or from the calibration registers. A
serial write to the AD7713 can write data to the control register
or the calibration registers.
Two different modes of operation are available, optimized for
different types of interface where the AD7713 can act either as
master in the system (it provides the serial clock) or as slave (an
external serial clock can be provided to the AD7713). These
two modes, labelled self-clocking mode and external clocking
mode, are discussed in detail in the following sections.
Self-Clocking Mode
The AD7713 is configured for its self-clocking mode by tying
the MODE pin high. In this mode, the AD7713 provides the
serial clock signal used for the transfer of data to and from the
AD7713. This self-clocking mode can be used with processors
that allow an external device to clock their serial port including
most digital signal processors and microcontrollers such as the
68HC11 and 68HC05. It also allows easy interfacing to serial
parallel conversion circuits in systems with parallel data commu-
nication, allowing interfacing to 74XX299 Universal Shift regis-
ters without any additional decoding. In the case of shift registers,
the serial clock line should have a pull-down resistor instead of
the pull-up resistor shown in Figure 10 and Figure 11.
Read Operation
Data can be read from either the output register, the control
register or the calibration registers. A0 determines whether the
data read accesses data from the control register or from the
output/calibration registers. This A0 signal must remain valid
for the duration of the serial read operation. With A0 high, data
is accessed from either the output register or from the calibra-
tion registers. With A0 low, data is accessed from the control
register.
The function of the
DRDY
line is dependent only on the output
update rate of the device and the reading of the output data reg-
ister.
DRDY
goes low when a new data word is available in the
3-STATE
SDATA (O)
SCLK (O)
RFS (I)
A0 (I)
DRDY (O)
MSB
LSB
t
3
t
2
t
4
t
5
t
6
t
9
t
10
t
8
t
7
Figure 10. Self-Clocking Mode, Output Data Read Operation
相關PDF資料 |
PDF描述 |
|---|---|
| AD7713 | Loop-Powered Signal Conditioning ADC(循環驅動LC2MOS信號調節A/D轉換器) |
| AD7714AN-3 | VARISTOR 30VRMS 0805 SMD |
| AD7714AN-5 | VARISTOR 40VRMS 1206 SMD |
| AD7714YRU | 3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714* | 3 V/5 V. CMOS. 500 uA Signal Conditioning ADC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7714 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714ACHIPS-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714ACHIPS-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714AN-3 | 制造商:Rochester Electronics LLC 功能描述:24-BIT SIGMA DELTA A/D IC - Bulk 制造商:Analog Devices 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。