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參數資料
| 型號： | AD7713SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Loop-Powered Signal Conditioning ADC |
| 中文描述： | 3-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件頁數： | 3/28頁 |
| 文件大小： | 516K |
| 代理商： | AD7713SQ |
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Parameter
REFERENCE INPUT
REF IN(+) – REF IN(–) Voltage
A, S Versions
1
Units
Conditions/Comments
+2.5 to AV
DD
/1.8
V min to V max
For Specified Performance. Part Is Functional with Lower
V
REF
Voltages
Input Sampling Rate, f
Normal-Mode 50 Hz Rejection
6
Normal-Mode 60 Hz Rejection
6
Common-Mode Rejection (CMR)
Common-Mode 50 Hz Rejection
6
Common-Mode 60 Hz Rejection
6
Common-Mode Voltage Range
10
DC Input Leakage Current @ +25
°
C
T
MIN
to T
MAX
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
V
INL
, Input Low Voltage
V
, Input High Voltage
MCLK IN Only
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
LOGIC OUTPUTS
V
OL
, Output Low Voltage
V
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
12
TRANSDUCER BURN-OUT
Current
Initial Tolerance @ +25
°
C
Drift
RTD EXCITATION CURRENTS
(RTD1, RTD2)
Output Current
Initial Tolerance @ +25
°
C
Drift
Initial Matching @ +25
°
C
Drift Matching
Line Regulation (AV
DD
)
Load Regulation
f
/512
100
100
100
150
150
AGND to AV
DD
10
1
dB min
dB min
dB min
dB min
dB min
V min to V max
pA max
nA max
For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz,
±
0.02
×
f
NOTCH
At DC
For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz,
±
0.02
×
f
NOTCH
±
10
μ
A max
0.8
2.0
V max
V min
0.8
3.5
V max
V min
0.4
4.0
±
10
9
V max
V min
μ
A max
pF typ
I
SINK
= 1.6 mA
I
SOURCE
= 100
μ
A
1
±
10
0.1
μ
A nom
% typ
%/
°
C typ
200
±
20
20
±
1
3
200
200
μ
A nom
% max
ppm/
°
C typ
% max
ppm/
°
C typ
nA/V max
nA/V max
Matching Between RTD1 and RTD2 Currents
Matching Between RTD1 and RTD2 Current Drift
AV
DD
= +5 V
SYSTEM CALIBRATION
AIN1, AIN2
Positive Full-Scale Calibration Limit
13
Negative Full-Scale Calibration Limit
13
Offset Calibration Limit
14, 15
Input Span
14
+(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
+0.8
×
V
REF
/GAIN
+(2.1
×
V
REF
)/GAIN
V max
V max
V max
V min
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
AIN3
Positive Full-Scale Calibration Limit
13
Offset Calibration Limit
15
Input Span
+(4.2
×
V
REF
)/GAIN
0 to V
REF
/GAIN
+3.2
×
V
REF
/GAIN
+(4.2
×
V
REF
)/GAIN
V max
V max
V min
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
NOTES
12
Guaranteed by design, not production tested.
13
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
14
These calibration and span limits apply provided the absolute voltage on the AIN1 and AIN2 analog inputs does not exceed AV
DD
+ 30 mV or go more negative
than AGND – 30 mV.
15
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
AD7713
–3–
REV. C
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