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參數(shù)資料
| 型號： | AD7713SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Loop-Powered Signal Conditioning ADC |
| 中文描述： | 3-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大小： | 516K |
| 代理商： | AD7713SQ |
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REV. C
–8–
AD7713
Pin
Mnemonic
Function
21
DRDY
Logic output. A falling edge indicates that a new output word is available for transmission. The
DRDY
pin
will return high upon completion of transmission of a full output word.
DRDY
is also used to indicate
when the AD7713 has completed its on-chip calibration sequence.
Serial Data. Input/Output with serial data being written to either the control register or the calibration
registers and serial data being accessed from the control register, calibration registers or the data register.
During an output data read operation, serial data becomes active after
RFS
goes low (provided
DRDY
is
low). During a write operation, valid serial data is expected on the rising edges of SCLK when
TFS
is low.
The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.
Digital Supply Voltage, +5 V. DV
DD
should not exceed AV
DD
by more than 0.3 V in normal operation.
Ground reference point for digital circuitry.
22
SDATA
23
DV
DD
DGND
24
TERMINOLOGY
INTEGRAL NONLINEARITY
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are zero scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transi-
tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB
above the last code transition (111 . . . 110 to 111 . . . 111). The
error is expressed as a percentage of full scale.
POSITIVE FULL-SCALE ERROR
Positive full-scale error is the deviation of the last code transi-
tion (111 . . . 110 to 111 . . . 111) from the ideal input full-scale
voltage. For AIN1(+) and AIN2(+), the ideal full-scale input
voltage is (AIN1(–) + V
REF
/GAIN – 3/2 LSBs) where AIN(–) is
either AIN1(–) or AIN2(–) as appropriate; for AIN3, the ideal
full-scale voltage is +4
×
V
REF
/GAIN – 3/2 LSBs. Positive full-
scale error applies to both unipolar and bipolar analog input
ranges.
UNIPOLAR OFFSET ERROR
Unipolar offset error is the deviation of the first code transition
from the ideal voltage. For AIN1(+) and AIN2(+), the ideal
input voltage is (AIN1(–) + 0.5 LSB); for AIN3, the ideal input
is 0.5 LSB when operating in the Unipolar Mode.
BIPOLAR ZERO ERROR
This is the deviation of the midscale transition (0111 . . . 111
to 1000 . . . 000) from the ideal input voltage. For AIN1(+) and
AIN2(+), the ideal input voltage is (AIN1(–) – 0.5 LSB); AIN3
can only accommodate unipolar input ranges.
BIPOLAR NEGATIVE FULL-SCALE ERROR
This is the deviation of the first code transition from the ideal
input voltage. For AIN1(+) and AIN2(+), the ideal input volt-
age is (AIN1(–) – V
REF
/GAIN + 0.5 LSB); AIN3 can only ac-
commodate unipolar input ranges.
POSITIVE FULL-SCALE OVERRANGE
Positive full-scale overrange is the amount of overhead available
to handle input voltages on AIN1(+) and AIN2(+) inputs
greater than (AIN1(–) + V
REF
/GAIN) or on AIN3 of greater
than +4
×
V
REF
/GAIN (for example, noise peaks or excess volt-
ages due to system gain errors in system calibration routines)
without introducing errors due to overloading the analog modu-
lator or to overflowing the digital filter.
NEGATIVE FULL-SCALE OVERRANGE
This is the amount of overhead available to handle voltages on
AIN1(+) and AIN2(+) below (AIN1(–) – V
REF
/GAIN) without
overloading the analog modulator or overflowing the digital filter.
OFFSET CALIBRATION RANGE
In the system calibration modes, the AD7713 calibrates its offset
with respect to the analog input. The offset calibration range
specification defines the range of voltages that the AD7713 can
accept and still calibrate offset accurately.
FULL-SCALE CALIBRATION RANGE
This is the range of voltages that the AD7713 can accept in the
system calibration mode and still calibrate full scale correctly.
INPUT SPAN
In system calibration schemes, two voltages applied in sequence
to the AD7713’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero to full scale that the AD7713 can
accept and still calibrate gain accurately.
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| AD7713 | Loop-Powered Signal Conditioning ADC(循環(huán)驅(qū)動LC2MOS信號調(diào)節(jié)A/D轉(zhuǎn)換器) |
| AD7714AN-3 | VARISTOR 30VRMS 0805 SMD |
| AD7714AN-5 | VARISTOR 40VRMS 1206 SMD |
| AD7714YRU | 3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD7714 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714ACHIPS-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714ACHIPS-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714AN-3 | 制造商:Rochester Electronics LLC 功能描述:24-BIT SIGMA DELTA A/D IC - Bulk 制造商:Analog Devices 功能描述: |
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