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參數資料
| 型號： | AD7713SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Loop-Powered Signal Conditioning ADC |
| 中文描述： | 3-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件頁數： | 22/28頁 |
| 文件大小： | 516K |
| 代理商： | AD7713SQ |
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REV. C
–22–
AD7713
SCLK (I)
SDATA (I)
TFS (I)
A0 (I)
MSB
BIT N
BIT N+1
t
32
t
26
t
30
t
27
t
36
t
35
t
35
t
36
Figure 13b. External Clocking Mode, Control/Calibration Register Write Operation (
TFS
Returns High During
Write Operation)
Data to be loaded to the AD7713 must be valid prior to the ris-
ing edge of the SCLK signal.
TFS
should return high during the
low time of SCLK. After
TFS
returns low again, the next bit of
the data word to be loaded to the AD7713 is clocked in on next
high level of the SCLK input. On the last active high time of the
SCLK input, the LSB is loaded to the AD7713.
SIMPLIFYING THE EXTERNAL CLOCKING MODE
INTERFACE
In many applications, the user may not require the facility of
writing to the on-chip calibration registers. In this case, the
serial interface to the AD7713 in external clocking modecan be
simplified by connecting the
TFS
line to the A0 input of the
AD7713 (see Figure 14). This means that any write to the de-
vice will load data to the control register (since A0 is low while
TFS
is low) and any read to the device will access data from the
output data register or from the calibration registers (since A0 is
high while
RFS
is low). It should be noted that in this arrange-
ment the user does not have the capability of reading from the
control register.
FOUR
INTERFACE
LINES
RFS
AD7713
SDATA
SCLK
TFS
A0
Figure 14. Simplified Interface with
TFS
Connected to A0
Another method of simplifying the interface is to generate the
TFS
signal from an inverted
RFS
signal. However, generating
the signals the opposite way around (
RFS
from an inverted
TFS
) will cause writing errors.
MICROCOMPUTER/MICROPROCESSOR INTERFACING
The AD7713’s flexible serial interface allows for easy interface
to most microcomputers and microprocessors. Figure 15 shows
a flowchart diagram for a typical programming sequence for
reading data from the AD7713 to a microcomputer while Figure
16 shows a flowchart diagram for writing data to the AD7713.
Figures 17, 18 and 19 show some typical interface circuits.
The flowchart of Figure 15 is for continuous read operations
from the AD7713 output register. In the example shown, the
DRDY
line is continuously polled. Depending on the micropro-
cessor configuration, the
DRDY
line may come to an interrupt
input in which case the
DRDY
will automatically generate an
interrupt without being polled. The reading of the serial buffer
could be anything from one read operation up to three read
START
CONFIGURE &
INITIALIZE μC/μP
SERIAL PORT
NO
YES
x3
BRING
RFS
LOW
REVERSE ORDER OF
BITS
DRDY
LOW
BRING
RFS
,
TFS
HIGH
POLL
DRDY
READ SERIAL BUFFER
BRING
RFS
HIGH
Figure 15. Flowchart for Continuous Read Operations to
the AD7713
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PDF描述 |
|---|---|
| AD7713 | Loop-Powered Signal Conditioning ADC(循環驅動LC2MOS信號調節A/D轉換器) |
| AD7714AN-3 | VARISTOR 30VRMS 0805 SMD |
| AD7714AN-5 | VARISTOR 40VRMS 1206 SMD |
| AD7714YRU | 3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714* | 3 V/5 V. CMOS. 500 uA Signal Conditioning ADC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7714 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714ACHIPS-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714ACHIPS-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| AD7714AN-3 | 制造商:Rochester Electronics LLC 功能描述:24-BIT SIGMA DELTA A/D IC - Bulk 制造商:Analog Devices 功能描述: |
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