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參數資料
| 型號： | AD7722AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 195 kSPS CMOS, Sigma-Delta ADC |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL/PARALLEL ACCESS, PQFP44 |
| 封裝： | MS-022AA, MQFP-44 |
| 文件頁數： | 4/24頁 |
| 文件大小： | 526K |
| 代理商： | AD7722AS |
AD7722
–4–
REV. 0
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Units
CLKIN Frequency
CLKIN Period (t
CLK
= 1/f
CLK
)
CLKIN Low Pulse Width
CLKIN High Pulse Width
CLKIN Rise Time
CLKIN Fall Time
FSI Low Time
FSI Setup Time
FSI Hold Time
CLKIN to SCO Delay
SCO Period
1
SCO Transition to FSO High Delay
SCO Transition to FSO Low Delay
SCO Transition to SDO Valid Delay
SCO Transition from FSI
2
SDO Enable Delay Time
SDO Disable Delay Time
DRDY
High Time
Conversion Time
1
DRDY
to
CS
Setup Time
CS
to
RD
Setup Time
RD
Pulse Width
Data Access Time after
RD
Falling Edge
3
Bus Relinquish Time after
RD
Rising Edge
CS
to
RD
Hold Time
RD
to
DRDY
High Time
SYNC/RESET Input Pulse Width
DVAL Low Delay from SYNC/RESET
SYNC/RESET Low Time Before CLKIN Rising
DRDY
High Delay after SYNC/RESET Low
DRDY
Low Delay after SYNC/RESET Low
1
DVAL High Delay after SYNC/RESET Low
1
CAL Setup Time
CAL Pulse Width
Calibration Delay from CAL High
Unipolar Input Calibration Time, (
UNI
= “0”)
1
t
37
Bipolar Input Calibration Time, (
UNI
= “1”)
1
Conversion Results Valid, (
UNI
= “0”)
1
Conversion Results Valid, (
UNI
= “1”)
1
f
CLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
t
31
t
34
t
35
t
36
0.3
0.067
0.45
×
t
1
0.45
×
t
1
5
5
2
20
20
12.5
0.08
15
3.33
0.55
×
t
1
0.55
×
t
1
MHz
μ
s
ns
ns
t
CLK
ns
ns
ns
t
CLK
ns
ns
ns
t
CLK
ns
ns
t
CLK
t
CLK
ns
ns
ns
ns
ns
ns
t
CLK
ns
ns
ns
ns
t
CLK
t
CLK
ns
t
CLK
t
CLK
t
CLK
t
CLK
t
CLK
t
CLK
40
2
4
4
3
10
10
8
2.5
45
30
30
10
2
64
0
0
t
CLK
+ 20
t
CLK
+ 40
t
CLK
+ 40
0
1
10
40
10
50
(8192 + 64)
8192
10
1
2
64
(3
×
8192 + 2
×
512)
(4
×
8192 + 3
×
512)
(3
×
8192 + 2
×
512 + 64)
(4
×
8192 + 3
×
512 + 64)
t
37
t
38
t
38
NOTES
1
Guaranteed by design.
2
Frame Sync is initiated on falling edge of CLKIN.
3
With
RD
synchronous to CLKIN t
22
, can be reduced up to 1 t
CLK
.
(AV
DD
= +5 V
6
5%, DV
DD
= +5 V
6
5%, AGND = DGND = 0 V, C
L
= 50 pF, T
A
= T
MIN
to T
MAX
,
f
CLKIN
= 12.5 MHz, SFMT = Logic Low or High, CFMT = Logic Low or High)
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相關代理商/技術參數 |
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| AD7722AS-ES | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD7722ASZ | 功能描述:IC ADC 16BIT 195KSPS 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
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| AD7723BS | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 19.2Msps 16-bit Parallel/Serial 44-Pin MQFP 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi |
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