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參數(shù)資料
型號: AD7722AS
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 16-Bit, 195 kSPS CMOS, Sigma-Delta ADC
中文描述: 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL/PARALLEL ACCESS, PQFP44
封裝: MS-022AA, MQFP-44
文件頁數(shù): 8/24頁
文件大小: 526K
代理商: AD7722AS
AD7722
–8–
REV. 0
PIN CONFIGURATION
44-Pin PQFP (S-44)
3
4
5
6
7
1
2
10
11
8
9
40
39
38
41
42
43
44
36
35 34
37
29
30
31
32
33
27
28
25
26
23
24
PIN 1
TOP VIEW
(Not to Scale)
12 13
14
15 16 17 18
19 20 21 22
AD7722
DGND/DB13
DGND/DB14
DGND/DB15
SYNC
CS
DGND
CAL
AGND
AGND
REF2
AV
DD
DGND/DB2
DGND/DB1
DGND/DB0
CFMT/
DRDY
DVAL/
RD
DGND
UNI
P/
S
AGND
AGND1
CLKIN
T
D
S
F
S
D
D
S
F
D
D
D
X
A
A
D
A
V
R
V
A
A
D
A
R
PARALLEL MODE PIN FUNCTION DESCRIPTION
Mnemonic
Pin No.
Description
DVAL/
RD
5
Read Input is a level sensitive logic input. The
RD
logic level is sensed on the rising edge of CLKIN.
This digital input can be used in conjunction with
CS
to read data from the device. The output data
bus is enabled when the rising edge of CLKIN senses a logic low level on
RD
if
CS
is also low. When
RD
is sensed high, the output data bits DB15–DB0 will be high impedance.
Data Ready Logic Output. A falling edge indicates a new output word is available to be read from out-
put data register. DRDY will return high upon completion of a read operation. If a read operation
does not occur between output updates, DRDY will pulse high for two CLKIN cycles before the next
output update. DRDY also indicates when conversion results are available after a SYNC or RESET
sequence and when completing a self-calibration.
Data Output Bit (MSB)
Data Output Bit
Data Output Bit
Data Output Bit
Data Output Bit
Data Output Bit
Data Output Bit
Data Output Bit
Data Output Bit
Data Output Bit
Data Output Bit
Data Output Bit
Data Output Bit
Data Output Bit
Data Output Bit
Data Output Bit (LSB)
CFMT/
DRDY
2
DGND/DB15
DGND/DB14
DGND/DB13
DGND/DB12
DGND/DB11
DGND/DB10
FSO/DB9
SDO/DB8
SCO/DB7
FSI/DB6
SFMT/DB5
DOE/DB4
TSI/DB3
DGND/DB2
DGND/DB1
DGND/DB0
31
32
33
34
35
36
37
38
40
41
42
43
44
1
2
3
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