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參數資料
| 型號： | AD7851AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit 333 kSPS Serial A/D Converter |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁數： | 13/36頁 |
| 文件大?。?/td> | 435K |
| 代理商： | AD7851AR |
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–13–
REV. A
AD7851
FINISHED
LAST
REGISTER
WRITE
OPERATION
OR
ABORT
YES
NO
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
READ CAL REGISTER
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1,
RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11
START
Figure 9. Flowchart for Reading from the Calibration
Registers
Adjusting the Offset Calibration Register
T he offset calibration register contains 16 bits, two leading zeros
and 14 data bits. By changing the contents of the offset register,
different amounts of offset on the analog input signal can be
compensated for. Increasing the number in the offset calibration
register compensates for negative offset on the analog input sig-
nal, and decreasing the number in the offset calibration register
compensates for positive offset on the analog input signal. T he
default value of the offset calibration register is 0010 0000 0000
0000 approximately. T his is not an exact value, but the value in
the offset register should be close to this value. Each of the 14
data bits in the offset register is binary weighted; the MSB has a
weighting of 5% of the reference voltage, the MSB-1 has a
weighting of 2.5%, the MSB-2 has a weighting of 1.25%, and so
on down to the LSB which has a weighting of 0.0006%.
T his gives a resolution of
±
0.0006% of V
REF
approximately.
More accurately the resolution is
±
(0.05
×
V
REF
)/2
13
volts =
±
0.015 mV, with a 2.5 V reference. T he maximum offset that
can be compensated for is
±
5% of the reference voltage, which
equates to
±
125 mV with a 2.5 V reference and
±
250 mV with a
5 V reference.
Q. If a +20 mV offset is present in the analog input signal and the
reference voltage is 2.5V, what code needs to be written to the
offset register to compensate for the offset
A. 2.5 V reference implies that the resolution in the offset reg-
ister is 5%
×
2.5 V/2
13
= 0.015 mV. +20 mV/0.015 mV =
1310.72; rounding to the nearest number gives 1311. In
binary terms this is 0101 0001 1111, therefore decrease the
offset register by 0101 0001 1111.
T his method of compensating for offset in the analog input sig-
nal allows for fine tuning the offset compensation. If the offset
on the analog input signal is known, there will be no need to
apply the offset voltage to the analog input pins and do a system
calibration. T he offset compensation can take place in software.
Adjusting the Gain Calibration Register
T he gain calibration register contains 16 bits, two leading 0s
and 14 data bits. T he data bits are binary weighted as in the off-
set calibration register. T he gain register value is effectively mul-
tiplied by the analog input to scale the conversion result over the
full range. Increasing the gain register compensates for a
smaller analog input range and decreasing the gain register com-
pensates for a larger input range. T he maximum analog input
range that the gain register can compensate for is 1.025 times
the reference voltage, and the minimum input range is 0.975
times
the reference voltage.
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| AD7851ARSZ | 功能描述:IC ADC 14BIT SRL 333KSPS 24SSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
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