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參數資料
| 型號： | AD7851AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit 333 kSPS Serial A/D Converter |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁數： | 25/36頁 |
| 文件大小： | 435K |
| 代理商： | AD7851AR |
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–25–
REV. A
AD7851
MODE 2 (3-Wire SPI/QSPI Interface Mode)
T his is the DE FAULT INT E RFACE MODE .
In Figure 35 below we have the timing diagram for Interface
Mode 2 which is the SPI/QSPI interface mode. Here the
SYNC
input is active low and may be pulsed or tied permanently low.
If
SYNC
is permanently low 16 clock pulses must be applied to
the SCLK pin for the part to operate correctly, and with a
pulsed
SYNC
input a continuous SCLK may be applied pro-
vided
SYNC
is low for only 16 SCLK cycles. In Figure 35 the
SYNC
going low disables the three-state on the DOUT pin.
T he first falling edge of the SCLK after the
SYNC
going low
clocks out the first leading zero on the DOUT pin. T he DOUT
pin is 3-stated again a time t
12
after the
SYNC
goes high. With
the DIN pin the data input has to be set up a time t
7
before the
SCLK rising edge as the part samples the input data on the
SCLK rising edge in this case. T he POLARIT Y pin may be
used to change the SCLK edge which the data is sampled on
and clocked out on. If resetting the interface is required, the
SYNC
must be taken high and then low.
DB0
DB10
3-STATE
3-STATE
DB12
DB13
DB14
DB15
DB11
DB12
DB0
DB10
DB11
DB13
DB14
DB15
t
3
= –0.4 t
CLKIN
MIN (NONCONTINUOUS SCLK) –/+0.4 t
SCLK
MIN/MAX (CONTINUOUS SCLK),
t
6
= 45 MAX, t
7
= 30ns
MIN, t
8
= 20 MIN, t
11
= 30 MIN (NONCONTINUOUS SCLK) ,
30/0.4 t
SCLK
= ns
MIN/MAX (CONTINUOUS SCLK)
POLARITY PIN
LOGIC HIGH
SYNC
(I/P)
1
6
2
3
4
5
16
SCLK (I/P)
t
9
t
5
t
11
t
3
t
10
t
12
DOUT (O/P)
t
8
DIN (I/P)
t
6
t
7
t
8
t
6
Figure 35. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation with DIN Input, DOUT Output and
SYNC
Input
(SM1 = SM2 = 0)
t
3
= –0.4 t
CLKIN
MIN (NONCONTINUOUS SCLK) –/+0.4 t
SCLK
MIN/MAX (CONTINUOUS SCLK),
t
6
= 45 MAX, t
7
= 30ns
MIN, t
8
= 20 MIN, t
11
= 30 MIN
DB0
DB10
3-STATE
3-STATE
DB12
DB13
DB14
DB15
DB11
DB12
DB0
DB10
DB11
DB13
DB14
DB15
POLARITY PIN
LOGIC HIGH
SYNC
(I/P)
1
6
2
3
4
5
16
SCLK (I/P)
t
9
t
5
t
11
t
3
t
10
t
12
DOUT (O/P)
t
8
DIN (I/P)
t
6
t
7
t
8
t
6
Figure 36. QSPI Mode 3 Timing Diagram for Read/Write Operation with
SYNC
Input Edge Triggered (SM1 = 0, SM2 = 1)
MODE 3 (QSPI Interface Mode)
Figure 36 shows the timing diagram for
Interface Mode 3. In
this mode the DSP is the master and the part is the slave. Here
the
SYNC
input is edge triggered from high to low, and the 16
clock pulses are counted from this edge. Since the clock pulses
are counted internally then the
SYNC
signal does not have to go
high after the 16th SCLK rising edge as shown by the dotted
SYNC
line in Figure 36. T hus a frame sync that gives a high
pulse, of one SCLK cycle minimum duration, at the beginning
of the read/write operation may be used. T he rising edge of
SYNC
enables the 3-state on the DOUT pin. T he falling edge
of
SYNC
disables the 3-state on the DOUT pin, and data is
clocked out on the falling edge of SCLK . Once
SYNC
goes
high, the 3-state on the DOUT pin is enabled. T he data input is
sampled on the rising edge of SCLK and thus has to be valid a
time t
7
before this rising edge. T he POLARIT Y pin may be
used to change the SCLK edge which the data is sampled on
and clocked out on. If resetting the interface is required, the
SYNC
must be taken high and then low.
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| AD7851ARS | 制造商:Analog Devices 功能描述:ADC Single SAR 333ksps 14-bit Serial 24-Pin SSOP 制造商:Analog Devices 功能描述:IC 14-BIT ADC |
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| AD7851ARSZ | 功能描述:IC ADC 14BIT SRL 333KSPS 24SSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
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