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參數(shù)資料
| 型號(hào)： | AD7851AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit 333 kSPS Serial A/D Converter |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁數(shù)： | 30/36頁 |
| 文件大小： | 435K |
| 代理商： | AD7851AR |
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AD7851
–30–
REV. A
(8XC51/L51)
/PIC17C42
P3.0/DT
P3.1/CK
AD7851
CONVST
CLKIN
SCLK
DIN
SYNC
SM1
SM2
POLARITY
OPTIONAL
7MHz/6MHz
BUSY
(
INT0
/P3.2)/INT
DV
FOR 8XC51/L51
DGND FOR PIC17C42
MASTER
SLAVE
OPTIONAL
Figure 45. 8XC51/PIC16C42 Interface
AD7851 to 68HC11/16/L11 / PIC16C42 Interface
Figure 46 shows the AD7851 SPI/QSPI interface to the
68HC11/16/L11/PIC16C42. T he
SYNC
line is not used and is
tied to DGND. T he
μ
Controller is configured as the master, by
setting the MST R bit in the SPCR to 1, and thus provides the
serial clock on the SCK pin. For all the
μ
Controllers, the CPOL
bit is set to 1 and for the 68HC11/16/L11, the CPHA bit is set
to 1. T he CLK IN and
CONVST
signals can be supplied from
the
μ
Controller or from separate sources. T he BUSY signal can
be used as an interrupt to tell the
μ
Controller when the conver-
sion is finished, then the reading and writing can take place. If
required the reading and writing can take place during conver-
sion and there will be no need for the BUSY signal in this case.
For no writing to the part then the DIN pin can be tied perma-
nently low. For the 68HC16 and the QSPI interface the SM2
pin should be tied high and the
SS
line tied to the
SYNC
pin.
T he microsequencer on the 68HC16 QSPI port can be used for
performing a number of read and write operations independent
of the CPU and storing the conversion results in memory with-
out taxing the CPU. T he typical sequence of events would be
writing to the control register via the DIN line setting a conver-
sion start and at the same time reading data from the previous
conversion on the DOUT line, wait for the conversion to be
finished (3.25
μ
s with 6 MHz CL K IN), and then repeat the
sequence. T he maximum serial frequency will be determined by
the data access and hold times of the
μ
Controllers and the
AD7851.
68HC11/L11/16
SCK
SS
AD7851
CONVST
CLKIN
SCLK
DOUT
BUSY
SM1
SM2
POLARITY
OPTIONAL
7MHz/6MHz
SYNC
MISO
DIN AT DGND FOR
NO WRITING TO PART
DV
FOR HC11, SPI
DGND FOR HC16, QSPI
MASTER
SLAVE
DIN
DV
DD
OPTIONAL
IRQ
MOSI
DV
DD
SPI
HC16, QSPI
Figure 46. 68HC11 and 68HC16 Interface
MICROPROCE SSOR INT E RFACING
In many applications, the user may not require the facility of
writing to the on-chip registers. T he user may just want to
hardwire the relevant pins to the appropriate levels and read the
conversion result. In this case the DIN pin can be tied low so
that the on-chip registers are never used. Now the part will op-
erate as a nonprogrammable analog to digital converter where
the
CONVST
is applied, a conversion is performed and the re-
sult may be read using the SCLK to clock out the data from the
output register on to the DOUT pin. Note that the DIN pin
cannot be tied low when using the two-wire interface mode of
operation.
T he SCLK can also be connected to the CLK IN pin if the user
does not want to have to provide separate serial and master
clocks in Interface Modes 1, 2, and 3. With this arrangement
the
SYNC
signal must be low for 16 SCLK cycles in Interface
Modes 1 and 2 for the read and write operations. For Interface
Mode 3 the
SYNC
can be low for more than 16 SCLK cycles
for the read and write operations. Note that in Interface Modes
4 and 5 the CLK IN and SCLK cannot be tied together as the
SCLK is an output and the CLK IN is an input.
DIN
DOUT
SYNC
CONVST
CLKIN
SCLK
AD7851
7 MHz/6MHz
MASTER CLOCK
SYNC
SIGNAL
TO GATE
THE SCLK
SERIAL DATA
OUTPUT
CONVERSION
START
Figure 44. Simplified Interface Diagram with DIN
Grounded and SCLK Tied to CLKIN
AD7851 to 8X C51/PIC17C42 Interface
Figure 45 shows the AD7851 interface to the 8X C51/PIC17C42.
T he 8X C51/PIC17C42 only run at 5 V. T he 8X C51 is in Mode
0 operation. T his is a two-wire interface consisting of the SCLK
and the DIN which acts as a bidirectional line. T he
SYNC
is
tied low. T he BUSY line can be used to give an interrupt driven
system but this would not normally be the case with the 8X C51/
PIC17C42. For the 8X C51 12 MHz version, the serial clock
will run at a maximum of 1 MHz so that the serial interface to
the AD7851 will only be running at 1 MHz. T he CLK IN signal
must be provided separately to the AD7851 from a port line on
the 8X C51 or from a source other than the 8X C51. Here the
SCLK cannot be tied to the CLK IN as the 8X C51 only pro-
vides a noncontinuous serial clock. T he
CONVST
signal can be
provided from an external timer or conversion can be started in
software if required. T he sequence of events would typically be
writing to the control register via the DIN line setting a conver-
sion start and the 2-wire interface mode (this would be per-
formed in two 8-bit writes), wait for the conversion to be
finished (3.25
μ
s with 6 MHz CLK IN), read the conversion re-
sult data on the DIN line (this would be performed in two 8-bit
reads), and then repeat the sequence. T he maximum serial fre-
quency will be determined by the data access and hold times of
the 8X C51/PIC16C42 and the AD7851.
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