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參數資料
| 型號： | AD7851AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit 333 kSPS Serial A/D Converter |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁數： | 19/36頁 |
| 文件大?。?/td> | 435K |
| 代理商： | AD7851AR |
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–19–
REV. A
AD7851
POWE R-UP T IME S
Using An E xternal Reference
When the AD7851 are powered up, the parts are powered up
from one of two conditions. First, when the power supplies are
initially powered up and, secondly, when the parts are powered
up from either a hardware or software power-down (see last
section).
When AV
DD
and DV
DD
are powered up, the AD7851 enters a
mode whereby the CONVST signal initiates a timeout followed
by a self-calibration. T he total time taken for this time-out and
calibration is approximately 35 ms—see
Calibration on Power-Up
in the
calibration
section of this data sheet. During power-up
the functionality of the
SLEEP
pin is disabled, i.e., the part will
not power down until the end of the calibration if
SLEEP
is tied
logic low. T he power-up calibration mode can be disabled if the
user writes to the control register before a
CONVST
signal is
applied. If the time out and self-calibration are disabled, then
the user must take into account the time required by the
AD7851 to power up before a self-calibration is carried out.
T his power-up time is the time taken for the AD7851 to power
up when power is first applied (300
μ
s typ) or the time it takes
the external reference to settle to the 14-bit level—whichever is
the longer.
T he AD7851 powers up from a full hardware or software
power-down in 5
μ
s typ. T his limits the throughput which the
part is capable of to 120 kSPS for the K Grade and 126 kSPS
for the A Grade when powering down between conversions. Fig-
ure 24 shows how power-down between conversions is imple-
mented using the
CONVST
pin. T he user first selects the
power-down between conversions option by using the
SLEEP
pin and the power management bits, PMGT 1 and PMGT 0, in
the control register. See last section. In this mode the AD7851
automatically enters a full power-down at the end of a conver-
sion, i.e., when BUSY goes low. T he falling edge of the next
CONVST
pulse causes the part to power up. Assuming the ex-
ternal reference is left powered up, the AD7851 should be ready
for normal operation 5
μ
s after this falling edge. T he rising edge
of
CONVST
initiates a conversion so the
CONVST
pulse
should be at least 5
μ
s wide. T he part automatically powers
down on completion of the conversion. Where the software con-
vert start is used, the part may be powered up in software before
a conversion is initiated.
5μs
3.25μs
t
CONVERT
POWER-UP
TIME
NORMAL
OPERATION
FULL
POWER-DOWN
POWER-UP
TIME
START CONVERSION ON RISING EDGE
POWER-UP ON FALLING EDGE
CONVST
BUSY
Figure 24. Using the CONVST Pin to Power Up the AD7851
for a Conversion
Using T he Internal (On-Chip) Reference
As in the case of an external reference, the AD7851 can power
up from one of two conditions, power-up after the supplies are
connected or power-up from hardware/software power-down.
When using the on-chip reference and powering up when AV
DD
and DV
DD
are first connected, it is recommended that the
power-up calibration mode be disabled as explained above.
When using the on-chip reference, the power-up time is effec-
tively the time it takes to charge up the external capacitor on the
REF
IN
/REF
OUT
pin. T his time is given by the equation:
t
UP
= 9
×
R
×
C
where
R
≈
150K and
C
= external capacitor.
T he recommended value of the external capacitor is 100nF;
this gives a power-up time of approximately 135 ms before a
calibration is initiated and normal operation should commence.
When C
REF
is fully charged, the power-up time from a hardware
or software power-down reduces to 5
μ
s. T his is because an
internal switch opens to provide a high impedance discharge
path for the reference capacitor during power-down—see Figure
25. An added advantage of the low charge leakage from the
reference capacitor during power-down is that even though the
reference is being powered down between conversions, the refer-
ence capacitor holds the reference voltage to within 0.5LSBs
with throughput rates of 100 samples/second and over with a
full power-down between conversions. A high input impedance
op amp like the AD707 should be used to buffer this reference
capacitor if it is being used externally. Note, if the AD7851 is
left in its powered-down state for more than 100 ms, the charge
on C
REF
will start to leak away and the power-up time will
increase. If this long power-up time is a problem, the user can
use a partial power-down for the last conversion so the reference
remains powered up.
AD7851
REF
IN
/REF
OUT
EXTERNAL
CAPACITOR
SWITCH OPENS
DURING POWER-DOWN
BUF
ON-CHIP
REFERENCE
TO OTHER
CIRCUITRY
Figure 25. On-Chip Reference During Power-Down
POWE R VS. T HROUGHPUT RAT E
T he main advantage of a full power-down after a conversion is
that it significantly reduces the power consumption of the part
at lower throughput rates. When using this mode of operation,
the AD7851 is only powered up for the duration of the conver-
sion. If the power-up time of the AD7851 is taken to be 5
μ
s
and it is assumed that the current during power up is 12 mA
typ, then power consumption as a function of throughput can
easily be calculated. T he AD7851 has a conversion time of
3.25
μ
s with a 6 MHz external clock. T his means the AD7851
consumes 12 mA typ for 8.25
μ
s in every conversion cycle if the
parts are powered down at the end of a conversion. T he graph,
Figure 26, shows the power consumption of the AD7851 as a
function of throughput. T able VII lists the power consump-
tion for various throughput rates.
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