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參數(shù)資料
| 型號(hào)： | AD7851AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit 333 kSPS Serial A/D Converter |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁(yè)數(shù)： | 18/36頁(yè) |
| 文件大小： | 435K |
| 代理商： | AD7851AR |
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AD7851
–18–
REV. A
INPUT FREQUENCY – kHz
–72
–74
–90
0.91
100
13.4
25.7
38.3
50.3
–76
–78
–80
–88
P
–82
–84
–86
63.5
74.8
87.4
AV
DD
= DV
DD
= 5.0V
100mV pk-pk SINEWAVE ON AV
DD
REF
IN
= 4.098 EXT REFERENCE
Figure 22. PSRR vs. Frequency
POWE R-DOWN OPT IONS
T he AD7851 provides flexible power management to allow the
user to achieve the best power performance for a given through-
put rate. T he power management options are selected by pro-
gramming the power management bits, PMGT 1 and PMGT 0,
in the control register and by use of the
SLEEP
pin. T able VI
summarizes the power-down options that are available and how
they can be selected by using either software, hardware or a
combination of both. T he AD7851 can be fully or partially pow-
ered down. When fully powered down, all the on-chip circuitry
is powered down and I
DD
is 1
μ
A typ. If a partial power-down is
selected, then all the on-chip circuitry except the reference is
powered down and I
DD
is 400
μ
A typ. T he choice of full or par-
tial power-down does not give any significant improvement in
throughput with a power-down between conversions. T his is dis-
cussed in the next section—
Power-Up Times
. But a partial
power-down does allow the on-chip reference to be used exter-
nally even though the rest of the AD7851 circuitry is powered
down. It also allows the AD7851 to be powered up faster after
a long power-down period when using the on-chip reference
(See
Power-Up Times
—
Using On-Chip Reference
).
When using the
SLEEP
pin, the power management bits
PMGT 1 and PMGT 0 should be set to zero (default status on
power-up). Bringing the
SLEEP
pin logic high ensures normal
operation, and the part does not power down at any stage. T his
may be necessary if the part is being used at high throughput
rates when it is not possible to power down between conver-
sions. If the user wishes to power down between conversions at
lower throughput rates (i.e., <100 kSPS for the AD7851) to
achieve better power performances, then the
SLEEP
pin should
be tied logic low.
If the power-down options are to be selected in software only,
then the
SLEEP
pin should be tied logic high. By setting the
power management bits PMGT 1 and PMGT 0 as shown in
T able VI, a Full Power-Down, Full Power-Up, Full Power-
Down Between Conversions, and a Partial Power-Down
Between Conversions can be selected.
A combination of hardware and software selection can also be
used to achieve the desired effect.
T able VI. Power Management Options
PMGT 1
Bit
PMGT 0
Bit
SLEEP
Pin
Comment
0
0
0
Full Power-Down Between
Conversions
(HW/SW)
Full Power-Up
(HW/SW)
Full Power-Down Between
Conversions (SW)
Full Power-Down
(SW)
Partial Power-Down Between
Conversions
(SW)
0
0
0
1
1
X
1
1
0
1
X
X
NOT E
SW = Software selection, HW = Hardware selection.
0V TO V
REF
INPUT
DIN AT DGND
=> NO WRITING
TO DEVICE
3-WIRE MODE
SELECTED
CURRENT, I = 12mA TYP
AV
DD
DV
DD
AIN(+)
AIN(–)
AMODE
C
REF1
C
REF2
SLEEP
DIN
DOUT
SYNC
SM1
SM2
CONVST
AGND
DGND
CLKIN
SCLK
REF
IN
/REF
OUT
POLARITY
AD7851
ANALOG
(+5V)
SUPPLY
0.01μF
0.1μF
10μF
DV
DD
UNIPOLAR RANGE
0.01μF
47nF
SERIAL MODE
SELECTION BITS
MASTER
CLOCK
INPUT
CONVERSION
START INPUT
SERIAL DATA OUTPUT
0.01μF
CAL
INTERNAL
REFERENCE
6/7MHz
OSCILLATOR
SERIAL CLOCK OUTPUT
285/333kHz PULSE
GENERATOR
OPTIONAL
EXTERNAL
REFERENCE
0.01μF
0.01μF
470nF
AUTO CAL ON
POWER-UP
REF198
AUTO POWER-
DOWN AFTER
CONVERSION
LOW POWER
μC/μP
Figure 23. Typical Low Power Circuit
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