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參數資料
| 型號： | AD7851AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit 333 kSPS Serial A/D Converter |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁數： | 24/36頁 |
| 文件大小： | 435K |
| 代理商： | AD7851AR |
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AD7851
–24–
REV. A
DB15
DB0
DB0
DB15
t
3
DIN (I/O)
t
3
t
11
t
6
1
16
16
1
t
5A
t
12
DIN BECOMES AN INPUT
3-STATE
t
6
t
11
DIN BECOMES AN OUTPUT
t
3
= –0.4 t
SCLK
MIN (NONCONTINUOUS SCLK) –/+0.4 t
SCLK
MIN/MAX (CONTINUOUS SCLK),
t
6
= 45 MAX, t
7
= 30ns
MIN, t
8
= 20
MIN
POLARITY PIN
LOGIC HIGH
SYNC
(I/P)
SCLK (I/P)
t
8
t
14
t
7
DATA WRITE
DATA READ
Figure 33. Timing Diagram for Read/Write Operation with DIN as an Input/Output (i.e., Interface Mode 1, SM1 = SM2 = 0)
DB15
DB0
DB0
DB15
DIN (I/O)
t
6
= 45 MAX, t
7
= 30ns
MIN, t
8
= 20
MIN,
t
13
= 90 MAX, t
14
= 50ns
MAX
6
1
16
16
1
t
13
t
6
DIN BECOMES AN INPUT
t
6
POLARITY PIN
LOGIC HIGH
SCLK (I/P)
t
8
t
14
t
7
DATA WRITE
DATA READ
Figure 34. Timing Diagram for Read/Write Operation with DIN as an Input/Output and
SYNC
Input Tied Low
(i.e., Interface Mode 1, SM1 = SM2 = 0)
DE T AILE D T IMING SE CT ION
MODE 1 (2-Wire 8051 Interface)
T he read and writing takes place on the DIN line and the con-
version is initiated by pulsing the
CONVST
pin (note that in
every write cycle the 2/
3
MODE bit must be set to 1). T he con-
version may be started by setting the
CONVST
bit in the con-
trol register to 1 instead of using the
CONVST
line.
Below in Figure 33 and in Figure 34 are the timing diagrams for
Interface Mode 1 in T able X I where we are in the 2-wire inter-
face mode. Here the DIN pin is used for both input and output
as shown. T he
SYNC
input is level triggered active low and can
be pulsed (Figure 33) or can be constantly low (Figure 34).
In Figure 33 the part samples the input data on the rising edge
of SCLK . After the 16th rising edge of SCLK the DIN is con-
figured as an output. When the
SYNC
is taken high the DIN is
3-stated. T aking
SYNC
low disables the 3-state on the DIN pin
and the first SCLK falling edge clocks out the first data bit.
Once the 16 clocks have been provided the DIN pin will auto-
matically revert back to an input after a time t
14
. Note that a
continuous SCLK shown by the dotted waveform in Figure 33
can be used provided that the
SYNC
is low for only 16 clock
pulses in each of the read and write cycles. T he POLARIT Y pin
may be used to change the SCLK edge which the data is
sampled on and clocked out on.
In Figure 34 the
SYNC
line is tied low permanently and this re-
sults in a different timing arrangement. With
SYNC
tied low
permanently the DIN pin will never be 3-stated. T he 16th rising
edge of SCLK configures the DIN pin as an input or an output
as shown in the diagram. Here no more than 16 SCLK pulses
must occur for each of the read and write operations.
If reading from and writing to the calibration registers in this in-
terface mode, all the selected calibration registers must be read
from or written to. T he read and write operations cannot be
aborted. When reading from the calibration registers, the DIN
pin will remain as an output for the full duration of all the cali-
bration register read operations. When writing to the calibration
registers, the DIN pin will remain as an input for the full dura-
tion of all the calibration register write operations.
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| AD7851ARSZ | 功能描述:IC ADC 14BIT SRL 333KSPS 24SSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7851ARSZ-REEL | 功能描述:IC ADC 14BIT SRL 333KSPS 24SSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
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