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參數資料
| 型號： | AD7851AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit 333 kSPS Serial A/D Converter |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁數： | 8/36頁 |
| 文件大小： | 435K |
| 代理商： | AD7851AR |
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AD7851
–8–
REV. A
PIN FUNCT ION DE SCRIPT ION
Pin
Mnemonic
Description
1
CONVST
Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and
starts conversion. When this input is not used, it should be tied to DV
DD
.
Busy Output. T he busy output is triggered high by the falling edge of
CONVST
or rising edge of
CAL
, and
remains high until conversion is completed. BUSY is also used to indicate when the AD7851 has completed
its on-chip calibration sequence.
Sleep Input/Low Power Mode. A logic 0 initiates a sleep and all circuitry is powered down including the in-
ternal voltage reference provided there is no conversion or calibration being performed. Calibration data is
retained. A logic 1 results in normal operation. See Power-Down section for more details.
Reference Input/Output. T his pin is connected to the internal reference through a series resistor and is the
reference source for the analog-to-digital converter. T he nominal reference voltage is 4.096 V and this ap-
pears at the pin. T his pin can be overdriven by an external reference or can be taken as high as AV
DD
.
When this pin is tied to AV
DD
, then the C
REF1
pin should also be tied to AV
DD
.
Analog Positive Supply Voltage, +5.0 V
±
5%.
Analog Ground. Ground reference for track/hold, reference and DAC.
Reference Capacitor (0.01
μ
F ceramic disc in parallel with a 470 nF NPO type). T his external capacitor is
used as a charge source for the internal DAC. T he capacitor should be tied between the pin and AGND.
Reference Capacitor (0.01
μ
F ceramic disc in parallel with a 470 nF NPO type). T his external capacitor is
used in conjunction with the on-chip reference. T he capacitor should be tied between the pin and AGND.
Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above
AV
DD
at any time, and cannot go below AIN(–) when the unipolar input range is selected.
Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above
AV
DD
at any time.
No Connect Pin.
Analog Mode Pin. T his pin allows two different analog input ranges to be selected. A logic 0 selects range 0
to V
REF
(i.e., AIN(+) – AIN(–) = 0 to V
REF
). In this case AIN(+) cannot go below AIN(–) and
AIN(–) cannot go below AGND. A logic 1 selects range –V
REF
/2 to +V
REF
/2 (i.e., AIN(+) – AIN(–) =
–V
REF
/2 to +V
REF
/2). In this case AIN(+) cannot go below AGND so that AIN(–) needs to be biased to
+V
REF
/2 to allow AIN(+) to go from 0 V to +V
REF
V.
Serial Clock Polarity. T his pin determines the active edge of the serial clock (SCLK ). T oggling this pin will
reverse the active edge of the serial clock (SCLK ). A logic 1 means that the serial clock (SCLK ) idles high
and a logic 0 means that the serial clock (SCLK ) idles low. It is best to refer to the timing diagrams and
T able X for the SCLK active edges.
Serial Mode Select Pin. T his pin is used in conjunction with the SM2 pin to give different modes of opera-
tion as described in T able X I.
Serial Mode Select Pin. T his pin is used in conjunction with the SM1 pin to give different modes of opera-
tion as described in T able X I.
Calibration Input. T his pin has an internal pull-up current source of 0.15
μ
A. A logic 0 on this pin resets all
logic and initiates a calibration on its rising edge. T here is the option of connecting a 10nF capacitor from
this pin to AGND to allow for an automatic self calibration on power-up. T his input overrides all other
internal operations.
Digital Supply Voltage, +5.0 V
±
5%.
Digital Ground. Ground reference point for digital circuitry.
Serial Data Output. T he data output is supplied to this pin as a 16-bit serial word.
Serial Data Input. T he data to be written is applied to this pin in serial form (16-bit word). T his pin can act
as an input pin or as a I/O pin depending on the serial interface mode the part is in (see T able X I).
Master Clock Signal for the device (6 MHz or 7 MHz). Sets the conversion and calibration times.
Serial Port Clock. Logic input/output. T he SCLK pin is configured as an input or output, dependent on the
type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and
SM2 pins. T he SCLK idles high or low depending on the state of the POLARIT Y pin.
T his pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync
in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see T able X I
)
.
2
BUSY
3
SLEEP
4
REF
IN
/
REF
OUT
5
6, 12 AGND
7
C
REF1
AV
DD
8
C
REF2
9
AIN(+)
10
AIN(–)
11
13
NC
AMODE
14
POLARIT Y
15
SM1
16
SM2
17
CAL
18
19
20
21
DV
DD
DGND
DOUT
DIN
22
23
CLK IN
SCLK
24
SYNC
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