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參數資料
型號: AD7851KR
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 14-Bit 333 kSPS Serial A/D Converter
中文描述: 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
封裝: MS-013AD, SOIC-24
文件頁數: 11/36頁
文件大小: 435K
代理商: AD7851KR
–11–
REV. A
AD7851
ST AT US RE GIST E R
T he arrangement of the status register is shown below. T he status register is a read-only register and contains 16 bits of data. T he
status register is selected by first writing to the control register and putting two 1s in RDSLT 1 and RDSLT 0. T he function of the
bits in the status register are described below. T he power-up status of all bits is 0.
WRITE TO CONTROL REGISTER
SETTING RDSLT0 = RDSLT1 = 1
READ STATUS REGISTER
START
Figure 6. Flowchart for Reading the Status Register
MSB
ZERO
BUSY
ZERO
ZERO
ZERO
ZERO
PMGT 1
PMGT 0
RDSLT 1
RDSLT 0
2/
3
MODE
X
C AL MD
CALSLT 1
CALSLT 0
ST C AL
L SB
Status Register Bit Function Description
Bit
Mnemonic
Comment
15
14
ZERO
BUSY
T his bit is always 0.
Conversion/Calibration Busy Bit. When this bit is 1, this indicates that there is a conversion or calibration
in progress. When this bit is 0, there is no conversion or calibration in progress.
T hese four bits are always 0.
13
12
11
10
9
8
7
6
5
ZERO
ZERO
ZERO
ZERO
PMGT 1
PMGT 0
ONE
ONE
2/
3
MODE
Power Management Bits. T hese bits along with the
SLEEP
pin will indicate if the part is in a power-down
mode or not. See T able VI in Power-Down Section for description.
Both these bits are always 1 indicating it is the status register that is being read. See T able II.
Interface Mode Select Bit. With this bit 0, the device is in Interface Mode 2. With this bit 1, the device is in
Interface Mode 1. T his bit is reset to 0 after every read cycle.
Don’t care bit.
Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a
system calibration is selected (see T able III).
Calibration Selection Bits and Start Calibration Bit. T he ST CAL bit is read as a 1 if a calibration is in
progress and as a 0 if there is no calibration in progress. T he CALSLT 1 and CALSLT 0 bits indicate
which of the calibration registers are addressed for reading and writing (see section on the Calibration
Registers for more details).
4
3
X
CALMD
2
1
0
CALSLT 1
CALSLT 0
ST CAL
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