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參數(shù)資料
型號: AD7851KR
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 14-Bit 333 kSPS Serial A/D Converter
中文描述: 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
封裝: MS-013AD, SOIC-24
文件頁數(shù): 5/36頁
文件大小: 435K
代理商: AD7851KR
–5–
REV. A
AD7851
T Y PICAL T IMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in In-
terface Modes 2 and 3. T o attain the maximum sample rate of
285 kHz in Interface Modes 2 and 3, reading and writing must
be performed during conversion. Figure 3 shows the timing dia-
gram for Interface Modes 4 and 5 with sample rate of 285 kHz.
At least 330 ns acquisition time must be allowed (the time from
the falling edge of BUSY to the next rising edge of
CONVST
)
before the next conversion begins to ensure that the part is
settled to the 14-bit level. If the user does not want to provide
the
CONVST
signal, the conversion can be initiated in software
by writing to the control register.
1.6mA
+2.1V
200μA
C
L
50pF
TO
OUTPUT
PIN
I
OL
I
OH
Figure 1. Load Circuit for Digital Output Timing
Specifications
DB15
DB0
DB11
POLARITY PIN LOGIC HIGH
SYNC
(I/P)
SCLK (I/P)
t
3
BUSY (O/P)
CONVST
(I/P)
t
2
t
5
t
11
t
6
t
9
t
10
1
5
6
16
t
12
DOUT (O/P)
DB0
DB11
t
8
DIN (I/P)
3-STATE
3-STATE
DB15
t
CONVERT
t
CONVERT
= 3.25μs MAX, t
= 100ns MIN,
t
5
7
= 30ns MIN
t
1
t
6
t
7
Figure 2. AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
POLARITY PIN LOGIC HIGH
SYNC (
O/P)
SCLK (O/P)
t
4
BUSY (O/P)
CONVST
(I/P)
t
2
t
5
t
11
t
12
t
9
t
10
1
5
6
16
DOUT (O/P)
DB0
DB11
t
8
DIN (I/P)
DB15
DB0
3-STATE
DB11
3-STATE
DB15
t
CONVERT
t
CONVERT
= 3.25μs MAX, t
= 100ns MIN,
t
5
7
= 30ns MIN
t
1
t
6
t
7
Figure 3. AD7851 Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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