- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄373920 > AD7851KR (ANALOG DEVICES INC) 14-Bit 333 kSPS Serial A/D Converter PDF資料下載
參數(shù)資料
| 型號(hào)： | AD7851KR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 14-Bit 333 kSPS Serial A/D Converter |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁(yè)數(shù)： | 23/36頁(yè) |
| 文件大小： | 435K |
| 代理商： | AD7851KR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)當(dāng)前第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)
–23–
REV. A
AD7851
SE RIAL INT E RFACE SUMMARY
T able IX details the five interface modes and the serial clock
edges from which the data is clocked out by the AD7851
(DOUT Edge) and that the data is latched in on (DIN Edge).
T he logic level of the POLARIT Y pin is shown and it is clear
that this reverses the edges.
In Interface Modes 4 and 5 the
SYNC
always clocks out the
first data bit and SCLK will clock out the subsequent bits.
In Interface Modes 1, 2, and 3 the
SYNC
is gated with the
SCLK and the POLARIT Y pin. T hus the
SYNC
may clock out
the MSB of data. Subsequent bits will be clocked out by the se-
rial clock, SCLK . T he conditions for the
SYNC
clocking out
the MSB of data is as follows:
With the POLARITY pin high the falling edge of
SYNC
will clock
out the MSB if the serial clock is low when the
SYNC
goes low.
With the POLARITY pin low the falling edge of
SYNC
will clock
out the MSB if the serial clock is high when the
SYNC
goes low.
T able IX . SCLK Active E dge for Different Interface Modes
Interface
Mode
POLARIT Y
Pin
DOUT
E dge
DIN
E dge
1, 2, 3
0
1
SCLK
↑
SCLK
↓
SCLK
↓
SCLK
↑
4, 5
0
1
SCLK
↓
SCLK
↑
SCLK
↑
SCLK
↓
Resetting the Serial Interface
When writing to the part via the DIN line there is the possibility
of writing data into the incorrect registers, such as the test regis-
ter for instance, or writing the incorrect data and corrupting the
serial interface. T he
SYNC
pin acts as a reset. Bringing the
SYNC
pin high resets the internal shift register. T he first data
bit after the next
SYNC
falling edge will now be the first bit of a
new 16-bit transfer. It is also possible that the test register con-
tents were altered when the interface was lost. T herefore, once
the serial interface is reset, it may be necessary to write the 16-
bit word 0100 0000 0000 0010 to restore the test register to its
default value. Now the part and serial interface are completely
reset. It is always useful to retain the ability to program the
SYNC
line from a port of the
μ
Controller/DSP to have the abil-
ity to reset the serial interface.
T able X summarizes the interface modes provided by the
AD7851. It also outlines the various
μ
P/
μ
C to which the par-
ticular interface is suited.
T he interface mode is determined by the serial mode selection
pins SM1 and SM2. Interface mode 2 is the default mode. Note
that Interface Mode 1 and 2 have the same combination of SM1
and SM2. Interface Mode 1 may only be set by programming
the control register (see section on control register). External
SCLK and
SYNC
signals (
SYNC
may be hardwired low) are
required for Interfaces Modes 1, 2, and 3. In Interface Modes 4
and 5 the AD7851 generates the SCLK and
SYNC
.
Some of the more popular
μ
Processors,
μ
Controllers, and the
DSP machines that the AD7851 will interface to directly are
mentioned here. T his does not cover all
μ
Cs,
μ
Ps and DSPs.
T he interface mode of the AD7851 that is mentioned here for a
specific
μ
C,
μ
P, or DSP is only a guide and in most cases an-
other interface mode may work just as well.
A more detailed timing description on each of the interface
modes follows.
T able X . Interface Mode Description
SM1
Pin
SM2
Pin
m
Processor/
m
Controller
Interface
Mode
0
0
8X C51
8X L51
PIC17C42
1 (2-Wire)
(DIN is an Input/
Output pin)
0
0
68HC11
68L11
2 (3-Wire, SPI/QSPI)
(Default Mode)
0
1
68HC16
PIC16C64
ADSP-21xx
DSP56000
DSP56001
DSP56002
DSP56L002
T MS320C30
3 (QSPI)
(External Serial
Clock, SCLK , and
External Frame Sync,
SYNC
, are required)
1
0
68HC16
4 (DSP is Slave)
(AD7851
generates a
noncontinuous
(16 clocks) Serial
Clock, SCLK , and the
Frame Sync,
SYNC
)
1
1
ADSP-21xx
DSP56000
DSP56001
DSP56002
DSP56L002
T MS320C20
T MS320C25
T MS320C30
T MS320C5X
T MS320LC5X
5 (DSP is Slave)
(AD7851
generates a
continuous Serial
Clock, SCLK , and the
Frame Sync,
SYNC
)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7853LARS | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7853L* | Single Supply V.35 Transceiver; Package: SO; No of Pins: 28; Temperature Range: -40°C to +85°C |
| AD7853L | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs(單電源,200kSPS 12位采樣A/D轉(zhuǎn)換器) |
| AD7853 | 3 V to 5 V Single Supply, 200 KSPS 12-Bit Sampling ADCs(單電源,200kSPS 12位采樣A/D轉(zhuǎn)換器) |
| AD7853AN | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7851KR-REEL | 制造商:Analog Devices 功能描述: |
| AD7851KRZ | 功能描述:IC ADC 14BIT SRL 333KSPS 24-SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7851KRZ3 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:14-Bit 333 kSPS Serial A/D Converter |
| AD7851KRZ-REEL | 功能描述:IC ADC 14BIT SRL 333KSPS 24-SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7851KRZ-REEL3 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:14-Bit 333 kSPS Serial A/D Converter |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。