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參數(shù)資料
| 型號： | AD7854L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit Sampling ADC(單電源,200kSPS 12位采樣A/D轉換器) |
| 中文描述： | 12位采樣ADC（單電源，速度高達200ksps的12位采樣的A / D轉換器） |
| 文件頁數(shù)： | 17/28頁 |
| 文件大小： | 268K |
| 代理商： | AD7854L |
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AD7854/AD7854L
REV. 0
–17–
POWE R-UP T IME S
Using an E xternal Reference
When the AD7854/AD7854L are powered up, the parts are
powered up from one of two conditions. First, when the power
supplies are initially powered up and, secondly, when the parts
are powered up from a software power-down (see last section).
When AV
DD
and DV
DD
are powered up, the AD7854/AD7854L
enters a mode whereby the
CONVST
signal initiates a timeout
followed by a self-calibration. T he total time taken for this time-
out and calibration is approximately 70 ms—see
Calibration on
Power-Up
in the calibration section of this data sheet. T he
power-up calibration mode can be disabled if the user writes to
the control register before a
CONVST
signal is applied. If the
timeout and self-calibration are disabled, then the user must
take into account the time required by the AD7854/AD7854L
to power up before a self-calibration is carried out. T his power-
up time is the time taken for the AD7854/AD7854L to power
up when power is first applied (300
μ
s typ) or the time it takes
the external reference to settle to the 12-bit level—whichever is
the longer.
T he AD7854/AD7854L powers up from a full software power-
down in 5
μ
s typ. T his limits the throughput which the part is
capable of to 100 kSPS for the AD7854 and 60 kSPS for the
AD7854L when powering down between conversions. Figure 21
shows how a full power-down between conversions is imple-
mented using the
CONVST
pin. T he user first selects the
power-down between conversions option by setting the power
management bits, PMGT 1 and PMGT 0, to 0 and 1 respectively
in the control register (see last section). In this mode the
AD7854/AD7854L automatically enters a full power-down at
the end of a conversion, i.e., when BUSY goes low. T he falling
edge of the next
CONVST
pulse causes the part to power up.
Assuming the external reference is left powered up, the
AD7854/AD7854L should be ready for normal operation 5
μ
s
after this falling edge. T he rising edge of
CONVST
initiates a
conversion so the
CONVST
pulse should be at least 5
μ
s wide.
T he part automatically powers down on completion of the con-
version. Where the software convert start is used, the part may
be powered up in software before a conversion is initiated.
t
CONVERT
5μs
4.6μs
POWER-UP
TIME
NORMAL
OPERATION
FULL
POWER-DOWN
POWER-UP
TIME
POWER-UP ON FALLING EDGE
START CONVERSION ON RISING EDGE
BUSY
CONVST
Figure 21. Using the CONVST Pin to Power Up the AD7854
for a Conversion
INPUT FREQUENCY – kHz
–78
–80
–900
100
20
P
40
60
–82
–84
–86
–88
80
AV
DD
= DV
DD
= 3.3V/5.0V,
100mVpk-pk SINE WAVE ON AV
DD
3.3V
5.0V
Figure 20. PSRR vs. Frequency
POWE R-DOWN OPT IONS
T he AD7854/AD7854L provides flexible power management to
allow the user to achieve the best power performance for a given
throughput rate. T he power management options are selected
by programming the power management bits, PMGT 1 and
PMGT 0, in the control register. T able VI summarizes the
power-down options that are available and how they can be se-
lected by programming the power management bits in the con-
trol register.
T he AD7854/AD7854L can be fully or partially powered down.
When fully powered down, all the on-chip circuitry is powered
down and I
DD
is 10
μ
A typ. If a partial power-down is selected,
then all the on-chip circuitry except the reference is powered
down and I
DD
is 400
μ
A typ with the external clock running.
Additional power savings may be made if the external clock is
off.
T he choice of full or partial power-down does not give any sig-
nificant improvement in the throughput rate which can be
achieved with a power-down between conversions. T his is dis-
cussed in the next section—
Power-Up Times
. But a partial
power-down does allow the on-chip reference to be used exter-
nally even though the rest of the AD7854/AD7854L circuitry is
powered down. It also allows the AD7854/AD7854L to be pow-
ered up faster after a long power-down period when using the
on-chip reference (See
Power-Up Times
section—
Using the
Internal (On-Chip) Reference
).
As can be seen from T able VI, the AD7854/AD7854L can be
programmed for normal operation, a full power-down at the end
of a conversion, a partial power-down at the end of a conversion
and finally a full power-down whether converting or not. T he
full and partial power-down at the end of a conversion can be
used to achieve a superior power performance at slower through-
put rates, in the order of 50 kSPS (see
Power vs. Throughput Rate
section of this data sheet).
T able VI. Power Management Options
PMGT 1 PMGT 0
Bit
Bit
Comment
0
0
1
1
0
1
0
1
Normal Operation
Full Power-Down After a Conversion
Full Power-Down
Partial Power-Down After a Conversion
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