- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373969 > AD9849KST (ANALOG DEVICES INC) CCD Signal Processors with Integrated Timing Driver PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9849KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processors with Integrated Timing Driver |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁(yè)數(shù)： | 26/36頁(yè) |
| 文件大小： | 347K |
| 代理商： | AD9849KST |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)當(dāng)前第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)
REV. 0
AD9848/AD9849
–26–
ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9848/AD9849 signal processing chain is shown in
Figure 15. Each processing step is essential in achieving a high-
quality image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1
μ
F series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.5 V, to be compatible with the 3 V analog
supply signal of the AD9848/AD9849.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low-frequency noise. The timing
shown in Figure 6 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference
level and data level of the CCD signal respectively. The place-
ment of the SHP and SHD sampling edges is determined by
the setting of the SHPPOSLOC and SHDPOSLOC registers
located at addr. 0xF0 and 0xF1 respectively. Placement of
these two clock signals is critical in achieving the best perfor-
mance from the CCD.
Input Clamp
A line-rate input clamping circuit is used to remove the CCD’s
optical black offset. This offset exists in the CCD’s shielded black
reference pixels. The AD9848/AD9849 removes this offset in
the input stage to minimize the effect of a gain change on the
system black level, usually called the “gain step.” Another
advantage of removing this offset at the input stage is to maxi-
mize system headroom. Some area CCDs have large black
level offset voltages, which, if not corrected at the input stage,
can significantly reduce the available headroom in the inter-
nal circuitry when higher VGA gain settings are used.
Horizontal timing examples are shown on the last page of the
“Applications Information” section. It is recommended that the
CLPDM pulse be used during valid CCD dark pixels. CLPDM
may be used during the optical black pixels, either together with
CLPOB or separately. The CLPDM pulse should be a minimum
of four pixels wide.
PxGA
The PxGA provides separate gain adjustment for the individual
color pixels. A programmable gain amplifier with four separate
values, the PxGA has the capability to “multiplex” its gain value
on a pixel-to-pixel basis (see Figure 17). This allows lower out-
put color pixels to be gained up to match higher output color
pixels. Also, the PxGA may be used to adjust the colors for
white balance, reducing the amount of digital processing that is
needed. The four different gain values are switched according to
the “Color Steering” circuitry. Seven different color steering
modes for different types of CCD color filter arrays are pro-
grammed in the AD9848/AD9849 AFE Register, ctlmode, at
addr. 0x06 (see Figure 16a–16g for timing examples). For
example, Mosaic Separate steering mode accommodates the
popular “Bayer” arrangement of Red, Green, and Blue filters
(see Figure 18).
0.1 F
0.1 F
0.1 F
1.0 F
1.0 F
0.1 F
0.1 F
0dB TO 36dB
CLPDM
CCDIN
DIGITAL
FILTER
CLPOB
DC RESTORE
OPTICAL BLACK
CLAMP
VGA
8-BIT
DAC
CLAMP LEVEL
REGISTER
8
VGA GAIN
REGISTER
10
CDS
INTERNAL
V
REF
2V FULL SCALE
–
2dB TO +10dB
10/12
PRECISION
TIMING
GENERATION
BYP1
BYP 2
SHP
SHD
PxGA
1.5V
OUTPUT
DATA
LATCH
REFT
REFB
DOUT
PHASE
V-H
TIMING
GENERATION
SHP SHD
DOUT
PHASE
CLPDM CLPOB PBLK
PBLK
1.0V
2.0V
DOUT
BYP 3
INPUT OFFSET
CLAMP
CML
AVDD
2
INTERNAL
BIASING
AD9848/AD9849
10-/12-BIT
ADC
Figure 15. Analog Front-End Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9851 | CMOS 180 MHz DDS/DAC Synthesizer |
| AD9852 | CMOS 300MHz Complete-DDS Synthesizer |
| AD9853 | Programmable Digital QPSK/16-QAM Modulator(可編程數(shù)字的四相移鍵控/16-正交幅度調(diào)制的調(diào)節(jié)器) |
| AD9854 | CMOS 300MHz Quadrature Complete-DDS |
| AD9858TLPCB | 1 GSPS Direct Digital Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9849KSTRL | 制造商:Analog Devices 功能描述:12 BIT 25 MSPS 5V AFE & T - Tape and Reel |
| AD9850 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS, 125 MHz Complete DDS Synthesizer |
| AD9850/CGPCB | 制造商:Analog Devices 功能描述:NCO/DDS, CMOS, 125MHZ COMPLETE DDS SYNTHESIZER - Bulk |
| AD9850/FSPCB | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR NCO/DDS, CMOS, 125MHZ COMPLETE DDS SYNTHESIZER 制造商:Analog Devices 功能描述:NCO/DDS, CMOS, 125MHZ COMPLETE DDS SYNTHESIZER - Bulk |
| AD9850BRS | 功能描述:IC DDS DAC W/COMP 125MHZ 28-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。