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參數(shù)資料
| 型號(hào)： | AD9849KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processors with Integrated Timing Driver |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁(yè)數(shù)： | 31/36頁(yè) |
| 文件大小： | 347K |
| 代理商： | AD9849KST |
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REV. 0
AD9848/AD9849
–31–
APPLICATIONS INFORMATION
External Circuit Configuration
The AD9848/AD9849 recommended circuit configuration for
External Mode is shown in Figure 21. All signals should be
carefully routed on the PCB to maintain low noise performance.
The CCD output signal should be connected to Pin 29 through
a 0.1
μ
F capacitor. The CCD timing signals H1–H4 and RG
should be routed directly to the CCD with minimum trace
lengths, as shown in Figures 22a and 22b. The digital outputs
and clock inputs are located on Pins 1–12 and Pins 36–48,
and should be connected to the digital ASIC, away from the
analog and CCD clock signals. The CLI signal from the ASIC
may be routed under the package to Pin 23. This will help separate
the CLI signal from the H1–H4 and RG signal routing.
Grounding and Decoupling Recommendations
As shown in Figure 21, a single ground plane is recommended
for the AD9848/AD9849. This ground plane should be as
continuous as possible, particularly around Pins 25 through 35.
This will ensure that all analog decoupling capacitors provide
the lowest possible impedance path between the power and
bypass pins and their respective ground pins. All decoupling
capacitors should be located as close as possible to the package
pins. Placing series resistors close to the digital output pins
(Pins 1–12, 47–48) may help reduce digital code transition
noise. If the digital outputs must drive a load larger than 20 pF,
buffering is recommended to minimize additional noise.
Power supply decoupling is very important in achieving low
noise performance. Figure 21 shows the local high frequency
decoupling capacitors, but additional capacitance is recom-
mended for lower frequencies. Additional capacitors and ferrite
beads can further reduce noise.
3V
DIGITAL
SUPPLY
SERIAL
INTERFACE
3
CCD
SIGNAL
CLOCK
INPUTS
6
0.1 F
36
35
34
33
32
31
30
29
28
27
26
25
3V
DRIVER
SUPPLY
13 14 15 16
CLOCK
INPUT
17 18 19 20 21 22 23 24
1
2
RG DRIVER
SUPPLY
3
H DRIVER
SUPPLY
4
5
6
7
8
9
10
11
3V
ANALOG
SUPPLY
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
TOP VIEW
(Not to Scale)
SL
REFT
REFB
CMLEVEL
AVSS3
AVDD3
BYP3
CCDIN
BYP2
BYP1
AVDD2
AVSS2
0.1 F
D2
D3
D4
D5
D6
1 F
DVSS3
DVDD3
1 F
D7
D8
D9
D10
AD9849
(MSB) D11
D
D
3V
ANALOG
SUPPLY
D
D
H
V
P
H
C
0.1 F
C
S
S
H
H
D
D
H
H
D
R
D
A
C
A
3V
ANALOG
SUPPLY
DATA
OUTPUTS
12
0.1 F 0.1 F 0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
HIGH-SPEED
CLOCKS
5
Figure 21. Recommend Circuit Configuration for External Mode
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