- 您現在的位置：買賣IC網 > PDF目錄373969 > AD9849KST (ANALOG DEVICES INC) CCD Signal Processors with Integrated Timing Driver PDF資料下載
參數資料
| 型號： | AD9849KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processors with Integrated Timing Driver |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數： | 30/36頁 |
| 文件大小： | 347K |
| 代理商： | AD9849KST |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當前第30頁第31頁第32頁第33頁第34頁第35頁第36頁
REV. 0
AD9848/AD9849
–30–
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets in
the signal chain and to track low-frequency variations in the CCD’s
black level. During the optical black (shielded) pixel interval on
each line, the ADC output is compared with a fixed black level
reference, selected by the user in the Clamp Level Register. The
value can be programmed between 0 LSB and 63.75 LSB on the
AD9848, and between 0 LSB and 255 LSB on the AD9849. The
clamp level can be programmed with 8-bit resolution. The result-
ing error signal is filtered to reduce noise, and the correction value
is applied to the ADC input through a D/A converter. Normally,
the optical black clamp loop is turned on once per horizontal line,
but this loop can be updated more slowly to suit a particular
application. If external digital clamping is used during the post
processing, the AD9848/AD9849 optical black clamping may be
disabled using Bit D2 in the OPRMODE Register. When the loop
is disabled, the Clamp Level Register may still be used to provide
programmable offset adjustment.
The CLPOB pulse should be placed during the CCD’s optical
black pixels. It is recommended that the CLPOB pulse duration
be at least 20 pixels wide to minimize clamp noise. Shorter pulse-
widths may be used, but clamp noise may increase, and the ability
to track low-frequency variations in the black level will be reduced.
See the section on Horizontal Clamping and Blanking and also
the Applications Information section for timing examples.
A/D Converter
The AD9848/AD9849 uses high-performance 10-bit/12-bit
ADC architecture, optimized for high speed and low power.
Differential Nonlinearity (DNL) performance is typically better
than 0.5 LSB. The ADC uses a 2 V input range. Better noise
performance results from using a larger ADC full-scale range.
See TPC 1–TPC 4 for typical linearity and noise performance
plots for the AD9848/AD9849.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9851 | CMOS 180 MHz DDS/DAC Synthesizer |
| AD9852 | CMOS 300MHz Complete-DDS Synthesizer |
| AD9853 | Programmable Digital QPSK/16-QAM Modulator(可編程數字的四相移鍵控/16-正交幅度調制的調節器) |
| AD9854 | CMOS 300MHz Quadrature Complete-DDS |
| AD9858TLPCB | 1 GSPS Direct Digital Synthesizer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9849KSTRL | 制造商:Analog Devices 功能描述:12 BIT 25 MSPS 5V AFE & T - Tape and Reel |
| AD9850 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS, 125 MHz Complete DDS Synthesizer |
| AD9850/CGPCB | 制造商:Analog Devices 功能描述:NCO/DDS, CMOS, 125MHZ COMPLETE DDS SYNTHESIZER - Bulk |
| AD9850/FSPCB | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR NCO/DDS, CMOS, 125MHZ COMPLETE DDS SYNTHESIZER 制造商:Analog Devices 功能描述:NCO/DDS, CMOS, 125MHZ COMPLETE DDS SYNTHESIZER - Bulk |
| AD9850BRS | 功能描述:IC DDS DAC W/COMP 125MHZ 28-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
發布緊急采購，3分鐘左右您將得到回復。