- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄373969 > AD9849KST (ANALOG DEVICES INC) CCD Signal Processors with Integrated Timing Driver PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9849KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processors with Integrated Timing Driver |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁(yè)數(shù)： | 27/36頁(yè) |
| 文件大小： | 347K |
| 代理商： | AD9849KST |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)當(dāng)前第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)
REV. 0
AD9848/AD9849
–27–
2
2
0
3
3
1
1
VD
NOTES
1. VD FALLING EDGE WILL RESET THE
PxGA
GAIN REGISTER STEERING TO "0101" LINE.
2. HD FALLING EDGES WILL ALTERNATE THE
PxGA
GAIN REGISTER STEERING BETWEEN "0101" AND "2323" LINES.
3. FLD STATUS IS IGNORED.
HD
1
1
0
X
X
PxGA
GAIN
REGISTER
FLD
0
ODD FIELD
EVEN FIELD
0
2
2
0
3
3
1
1
1
1
0
0
0
0
Figure 16a. Mosaic Separate Mode
0
0
0
1
1
1
1
VD
NOTES
1. FLD FALLING EDGE (START OF ODD FIELD) WILL RESET THE
PxGA
GAIN REGISTER STEERING TO "0101" LINE.
2. FLD RISING EDGE (START OF EVEN FIELD) WILL RESET THE
PxGA
GAIN REGISTER STEERING TO "2323" LINE.
3. HD FALLING EDGES WILL RESET THE
PxGA
GAIN REGISTER STEERING TO EITHER "0" (FLD = ODD) OR "2" (FLD = EVEN).
HD
1
1
0
X
X
PxGA
GAIN
REGISTER
FLD
0
ODD FIELD
EVEN FIELD
0
2
2
2
3
3
3
3
3
3
2
2
2
0
Figure 16b. Mosaic Interlaced Mode
1
1
0
2
2
1
1
VD
NOTES
1. VD FALLING EDGE WILL RESET THE
PxGA
GAIN REGISTER STEERING TO "0101" LINE.
2. HD FALLING EDGES WILL ALTERNATE THE
PxGA
GAIN REGISTER STEERING BETWEEN "0101" AND "1212" LINES.
3. ALL FIELDS WILL HAVE THE SAME
PxGA
GAIN STEERING PATTERN (FLD STATUS IS IGNORED).
HD
1
1
0
X
X
PxGA
GAIN
REGISTER
FLD
0
ODD FIELD
EVEN FIELD
0
1
1
0
2
2
1
1
1
1
0
0
0
0
Figure 16c. Mosaic Repeat Mode
0
2
0
1
0
0
1
VD
NOTES
1. EACH LINE FOLLOWS "012012" STEERING PATTERN.
2. VD AND HD FALLING EDGES WILL RESET THE
PxGA
GAIN REGISTER STEERING TO "0".
3. FLD STATUS IS IGNORED.
HD
1
0
2
X
X
PxGA
GAIN
REGISTER
FLD
0
ODD FIELD
EVEN FIELD
2
0
2
0
1
0
0
1
1
0
2
0
2
0
Figure 16d. Three-Color Mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9851 | CMOS 180 MHz DDS/DAC Synthesizer |
| AD9852 | CMOS 300MHz Complete-DDS Synthesizer |
| AD9853 | Programmable Digital QPSK/16-QAM Modulator(可編程數(shù)字的四相移鍵控/16-正交幅度調(diào)制的調(diào)節(jié)器) |
| AD9854 | CMOS 300MHz Quadrature Complete-DDS |
| AD9858TLPCB | 1 GSPS Direct Digital Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9849KSTRL | 制造商:Analog Devices 功能描述:12 BIT 25 MSPS 5V AFE & T - Tape and Reel |
| AD9850 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:CMOS, 125 MHz Complete DDS Synthesizer |
| AD9850/CGPCB | 制造商:Analog Devices 功能描述:NCO/DDS, CMOS, 125MHZ COMPLETE DDS SYNTHESIZER - Bulk |
| AD9850/FSPCB | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR NCO/DDS, CMOS, 125MHZ COMPLETE DDS SYNTHESIZER 制造商:Analog Devices 功能描述:NCO/DDS, CMOS, 125MHZ COMPLETE DDS SYNTHESIZER - Bulk |
| AD9850BRS | 功能描述:IC DDS DAC W/COMP 125MHZ 28-SSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。