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參數(shù)資料
| 型號(hào)： | AD9858BSV |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | 1 GSPS Direct Digital Synthesizer |
| 中文描述： | DSP-NUM CONTROLLED OSCILLATOR, PQFP100 |
| 封裝： | PLASTIC, MS-026AED-HD, TQFP-100 |
| 文件頁(yè)數(shù)： | 20/32頁(yè) |
| 文件大小： | 1412K |
| 代理商： | AD9858BSV |
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AD9858
SYSCLK serves as the sample clock for the DAC and is fed to a
divide-by-8 frequency divider to produce SYNCLK. SYNCLK is
provided to the user on the SYNCLK pin. This enables
synchronization of external hardware with the AD9858’s
internal DDS clock. External hardware that is synchronized to
the SYNCLK signal can then be used to provide the frequency
update (FUD) signal to the AD9858. The FUD signal and
SYNCLK are used to transfer the internal buffer register
contents into the memory registers of the device. Figure 33
Rev. A | Page 20 of 32
shows a block diagram of the synchronization methodology,
and Figure 34 shows an I/O synchronization timing diagram.
Note that SYNCLK is also used to synchronize the assertion of
the profile select pins (PS0, PS1). The FUD, PS0, and PS1 pins
must be set up and held around the rising edge of SYNCLK.
These device inputs are designed for zero hold time and 3.5 ns
setup time.
U
REGISTER
MEMORY
EDGE
DETECTION
LOGIC
REFCLK
P0, P1
FUD
SYNCLK
0
2 GHz DIVIDER
DISABLE
SYNCLK
DISABLE
TO CORE LOGIC
BUFFER
MEMORY
÷ 2
1
0
1
0
D
Q
WR
ADDR
DATA
SYNCLK
D
Q
0
÷ 8
Figure 33. I/O Synchronization Block Diagram
SYNCLK
SYSCLK
FUD REGISTERED
FUD EDGE DETECTED
FUD REGISTERED
FUD EDGE DETECTED
VALUE 2
VALUE 1
IO BUFFER
MEMORY
CONTROL
REGISTER
DATA
VALUE 0
VALUE 1
VALUE 2
(ASYNCHRONOUSLY LOADED VIA I/O PORT)
FUD
*
*
FUD IS AN INPUT PROVIDED BY THE USER THAT MUST BE SET UP AND HELD AROUND RISING EDGES OF SYNCLK. THE OCCURRENCE OF
THE RISING EDGE OF SYNCLK DURING THE HIGH STATE OF THE UPDATEREGS SIGNAL CAUSES THE BUFFER MEMORY CONTENTS TO BE
TRANSFERRED INTO THE CONTROL REGISTERS. SIMILARLY, A STATE CHANGE ON THE PS0 OR PS1 PINS IS EQUIVALENT TO ASSERTING A VALID
FUD SEQUENCE. NOTE: I/O UPDATES ARE SYNCHRONOUS TO THE SYNCLK SIGNAL, REGARDLESS OF THE SYNCHRONIZATION MODE SELECTED.
(ASYNCHRONOUSLY LOADED VIA I/O PORT)
0
Figure 34. I/O Synchronization Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9858BSVZ | 功能描述:IC DDS DAC 10BIT 1GSPS 100-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9858FDPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
| AD9858PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
| AD9858TLPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
| AD9858XSV | 制造商:Analog Devices 功能描述: |
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