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參數(shù)資料
| 型號： | AD9858BSV |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | 1 GSPS Direct Digital Synthesizer |
| 中文描述： | DSP-NUM CONTROLLED OSCILLATOR, PQFP100 |
| 封裝： | PLASTIC, MS-026AED-HD, TQFP-100 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大小： | 1412K |
| 代理商： | AD9858BSV |
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AD9858
Parameter
Rev. A | Page 5 of 32
Temp
Test
Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
IV
IV
IV
IV
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Minimum Clock Pulse Width Low (t
PWL
)
Minimum Clock Pulse Width High (t
PWH
)
Maximum Clock Rise/Fall Time
Minimum Data Setup Time (t
DS
)
Mimimum Data Hold Time (t
DH
)
Maximum Data Valid Time (t
DV
)
Parallel Control Bus
WR Minimum Low Time
WR Minimum High Time
WR Minimum Period
Address to WR Setup (T
ASU
)
Address to WR Setup (T
AHU
)
Data to WR Setup (T
DSU
)
Data to WR Hold (T
DHU
)
Miscellaneous Timing Specifications
REFCLK to SYNCLK
FUD to SYNCLK Setup Time
FUD to SYNCLK Hold Time
REFCLK to SYNCLK Delay
FUD Rising Edge to Frequency Change
Single Tone Mode
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
5.5
15
7
0
3
6
9
3
0
3.5
0
4
0
2.5
2.5
10
1
20
3
83
MHz
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
sysclk
cycles
sysclk
cycles
sysclk
cycles
Linear Sweep Mode
25°C
IV
99
FUD Rising Edge to Phase Offset Change
25°C
IV
83
1
The reference clock input is configured to accept a differential or single-ended sine wave input or a 3 V CMOS-level pulse input.
2
REFCLK input is internally dc biased. AC coupling should be used.
3
Reference clock frequency is selected to ensure second harmonic is out of the bandwidth of interest.
4
PD inputs sent @ 400 MHz, with divide-by-4 enabled.
5
The charge pump current is programmable in eight discrete steps, minimum value assumes current sharing.
6
For 0.75 V < V
CP
< CPV
DD
– 0.75 V.
7
These differential inputs are internally dc biased. AC coupling should be used.
8
The charge pump supply voltage can range from 4.75 V to 5.25 V.
9
Output interface is differential open collector.
10
For 1 dB output compression; input power measured at 50 .
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9858BSVZ | 功能描述:IC DDS DAC 10BIT 1GSPS 100-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9858FDPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
| AD9858PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
| AD9858TLPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
| AD9858XSV | 制造商:Analog Devices 功能描述: |
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