- 您現在的位置：買賣IC網 > PDF目錄373969 > AD9866CHIPS (ANALOG DEVICES INC) Broadband Modem Mixed Signal Front End PDF資料下載
參數資料
| 型號： | AD9866CHIPS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, UUC |
| 文件頁數： | 28/48頁 |
| 文件大?。?/td> | 1647K |
| 代理商： | AD9866CHIPS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
AD9866
TRANSMIT PATH
The AD9866 (or AD9865) transmit path consists of a selectable
digital 2×/4× interpolation filter, a 12-bit (or 10-bit) TxDAC,
and a current-output amplifier (IAMP), as shown in Figure 59.
Note that the additional two bits of resolution offered by the
AD9866 (vs. the AD9865) result in a 10 dB to 12 dB reduction
in the pass-band noise floor. The digital interpolation filter
relaxes the Tx analog filtering requirements by simultaneously
reducing the images from the DAC reconstruction process
while increasing the analog filter’s transition band. The digital
interpolation filter can also be bypassed, resulting in lower
digital current consumption.
Rev. 0 | Page 28 of 48
10
AD9865/AD9866
0 TO –7.5dB
0
0 TO –12dB
2-4X
IOUT_G+
IOUT_N+
IOUT_N–
IOUT_G–
IAMP
I
I
TXCLK
TXEN/SYNC
ADIO[11:6]/
Tx[5:0]
ADIO[11:6]/
Rx[5:0]
TxDAC
Figure 59. Functional Block Diagram of Tx Path
DIGITAL INTERPOLATION FILTERS
The input data from the Tx port can be fed into a selectable
2×/4× interpolation filter or directly into the TxDAC (for a half-
duplex only). The interpolation factor for the digital filter is set
via SPI Reg. 0x0C with the settings shown in Table 18. The
maximum input word rate, f
DATA
, into the interpolation filter is
80 MSPS; the maximum DAC update rate is 200 MSPS. There-
fore, applications with input word rates at or below 50 MSPS
can benefit from 4× interpolation, while applications with input
word rates between 50 MSPS and 80 MSPS can benefit from
2× interpolation.
Table 18. Interpolation Factor Set via SPI Reg. 0x0C
Bits [7:6]
Interpolation Factor
00
4
01
2
10
1 (half-duplex only)
11
Do not use
The interpolation filter consists of two cascaded half-band filter
stages with each stage providing 2× interpolation. The first stage
filter consists of 43 taps. The second stage filter, operating at the
higher data rate, consists of 11 taps. The normalized
wide band
and pass-band filter responses (relative f
DATA
) for the 2× and
4× low-pass interpolation filters are shown in Figure 60 and
Figure 61, respectively. Note that these responses also include
the inherent sinc(x) from the TxDAC reconstruction process
and can be used to estimate any post analog filtering
requirements.
The pipeline delays of the 2× and 4× filter responses are 21.5
and 24 clock cycles, respectively, relative to f
DATA
. The filter delay
is also taken into consideration for applications configured for a
half-duplex interface with the half-duplex power-down mode
enabled. This feature allows the user to set a programmable
delay that powers down the TxDAC and IAMP only after the
last Tx input sample has propagated through the digital filter.
See the Power Control section for more details.
0
NORMALIZED FREQUENCY (Relative to
f
DATA
)
W
0
10
1.25
2.00
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
1.75
0.75
1.00
1.50
WIDE BAND
0.50
0.25
P
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
PASS BAND
–1.0dB @ 0.441
f
DATA
Figure 60. Frequency Response of 2× Interpolation Filter
(Normalized to f
DATA
)
0
NORMALIZED FREQUENCY (Relative to
f
DATA
)
W
0
10
2.5
4.0
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
3.5
1.5
2.0
3.0
WIDE BAND
1.0
0.5
P
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
PASS BAND
–1.0dB @ 0.45
f
DATA
Figure 61. Frequency Response of 4× Interpolation Filter
(Normalized to f
DATA
)
TxDAC AND IAMP ARCHITECTURE
The Tx path contains a TxDAC along with a current amplifier,
IAMP. The TxDAC reconstructs the output of the interpolation
filter and sources a differential current output that can either be
directed to an external load or fed into the IAMP for further
amplification. The TxDAC’s and IAMPS’s peak current outputs
are digitally programmable over a 0 to 7.5 dB and 0 to 19.5
dB range, respectively, in 0.5 dB increments. Note that this
assumes default register settings for Reg. 0x10 and Reg. 0x11.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9866 | Broadband Modem Mixed Signal Front End |
| AD9866-EB | Broadband Modem Mixed Signal Front End |
| AD9866BCP | Broadband Modem Mixed Signal Front End |
| AD9870 | IF Digitizing Subsystem |
| AD9870EB | IF Digitizing Subsystem |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9866-EB | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:12B MXFE CONVERTER FOR BROADBAND MODEMS - Bulk |
| AD9867 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9867BCPZ | 功能描述:IC MXFE 75MSPS FOR TX/RX 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9867BCPZRL | 功能描述:IC MXFE 75MSPS FOR TX/RX 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9867-EBZ | 制造商:Analog Devices 功能描述:12B MXFE CONVERTER FOR BROADBAND MODEMS - Bulk |
發布緊急采購，3分鐘左右您將得到回復。